Searched refs:MidVT (Results 1 – 3 of 3) sorted by relevance
/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 3989 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt); in getPromotedVectorElementType() local 3990 assert(TLI.isTypeLegal(MidVT) && "unexpected"); in getPromotedVectorElementType() 3991 return MidVT; in getPromotedVectorElementType() 4257 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4262 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op)); in PromoteNode() 4290 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4291 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() 4311 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps); in PromoteNode() 4337 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT); in PromoteNode() local 4338 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements(); in PromoteNode() [all …]
|
D | LegalizeFloatTypes.cpp | 484 EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32); in SoftenFloatRes_FP16_TO_FP() local 486 SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op, in SoftenFloatRes_FP16_TO_FP()
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 8070 MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16); in performConcatVectorsCombine() local 8071 SmallVector<int, 8> Mask(MidVT.getVectorNumElements()); in performConcatVectorsCombine() 8076 MidVT, dl, in performConcatVectorsCombine() 8077 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine() 8078 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
|