| /external/clang/test/Modules/Inputs/stress1/ |
| D | common.h | 10 namespace N00 {
31 struct S00 : N00::S00 {};
45 struct S00 : N00::S00 {
46 using N00::S00::S00;
52 using namespace N00;
|
| D | merge00.h | 22 inline int g() { return N00::S00('a').method00('b') + (int)S00(42) + function00(42); } in g()
26 inline N00::S01 h() { return N00::S01(); } in h()
|
| D | m01.h | 8 inline N00::S01 m01_special_members() { return N00::S01(); } in m01_special_members()
|
| /external/clang/test/Modules/ |
| D | stress1.cpp | 131 int f() { return N01::S00('a').method00('b') + (int)N00::S00(42) + function00(42) + g(); } in f()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1711 SDValue N00 = N0.getOperand(0); in visitADD() local
1716 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) in visitADD()
1718 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), in visitADD()
3408 SDValue N00 = N0->getOperand(0); in MatchBSwapHWordLow() local
3409 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
3410 if (!N00.getNode()->hasOneUse()) in MatchBSwapHWordLow()
3412 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); in MatchBSwapHWordLow()
3415 N00 = N00.getOperand(0); in MatchBSwapHWordLow()
3430 if (N00 != N10) in MatchBSwapHWordLow()
3451 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00); in MatchBSwapHWordLow()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1297 SDValue N00 = N0.getOperand(0); in combineShlAddConstant() local
1301 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && in combineShlAddConstant()
1302 isa<ConstantSDNode>(N00.getOperand(1))) { in combineShlAddConstant()
1305 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, in combineShlAddConstant()
1306 N00.getOperand(0), N01), in combineShlAddConstant()
1308 N00.getOperand(1), N01)); in combineShlAddConstant()
1393 SDValue N00 = N0.getOperand(0); in visitADD() local
1398 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) in visitADD()
1400 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), in visitADD()
2546 SDValue N00 = N0->getOperand(0); in MatchBSwapHWordLow() local
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4685 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); in LowerMUL() local
4690 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
6607 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local
6610 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
6788 SDValue N00 = N0.getOperand(0); in PerformORCombine() local
6811 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, in PerformORCombine()
6839 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, in PerformORCombine()
6853 Res = DAG.getNode(ISD::SRL, DL, VT, N00, in PerformORCombine()
6864 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && in PerformORCombine()
6868 SDValue ShAmt = N00.getOperand(1); in PerformORCombine()
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 26263 SDValue N00 = N0->getOperand(0); in combineBitcast() local
26264 if (N00.getValueType() == MVT::i32) in combineBitcast()
26265 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00); in combineBitcast()
27696 SDValue N00 = N0.getOperand(0); in combineShiftLeft() local
27712 if (N00.getOpcode() == X86ISD::SETCC_CARRY) { in combineShiftLeft()
27714 } else if (N00.getOpcode() == ISD::SIGN_EXTEND && in combineShiftLeft()
27715 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { in combineShiftLeft()
27717 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND || in combineShiftLeft()
27718 N00.getOpcode() == ISD::ANY_EXTEND) && in combineShiftLeft()
27719 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { in combineShiftLeft()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6700 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local
6705 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
9130 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local
9133 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
9364 SDValue N00 = N0.getOperand(0); in PerformORCombine() local
9387 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, in PerformORCombine()
9415 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, in PerformORCombine()
9429 Res = DAG.getNode(ISD::SRL, DL, VT, N00, in PerformORCombine()
9440 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && in PerformORCombine()
9444 SDValue ShAmt = N00.getOperand(1); in PerformORCombine()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2270 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local
2275 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
7962 SDValue N00 = N0.getOperand(0); in performSRLCombine() local
7966 DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(32, 16))) in performSRLCombine()
7969 DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(64, 32))) in performSRLCombine()
8063 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
8065 EVT N00VT = N00.getValueType(); in performConcatVectorsCombine()
8077 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 13075 SDValue N00 = N0.getOperand(0); in PerformSHLCombine() local
13076 if (N00.getOpcode() == X86ISD::SETCC_CARRY || in PerformSHLCombine()
13077 ((N00.getOpcode() == ISD::ANY_EXTEND || in PerformSHLCombine()
13078 N00.getOpcode() == ISD::ZERO_EXTEND) && in PerformSHLCombine()
13079 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { in PerformSHLCombine()
13085 N00, DAG.getConstant(Mask, VT)); in PerformSHLCombine()
14048 SDValue N00 = N0.getOperand(0); in PerformZExtCombine() local
14049 if (N00.getOpcode() != X86ISD::SETCC_CARRY) in PerformZExtCombine()
14056 N00.getOperand(0), N00.getOperand(1)), in PerformZExtCombine()
|