Searched refs:N10 (Results 1 – 8 of 8) sorted by relevance
| /external/clang/test/Modules/ |
| D | namespaces.cpp | 49 namespace N10 { namespace
69 int &ir3 = N10::f(17); in testMergedMerged()
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| /external/clang/test/Modules/Inputs/ |
| D | namespaces-right.h | 46 namespace N10 {
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| D | namespaces-left.h | 57 namespace N10 {
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| /external/clang/test/SemaTemplate/ |
| D | instantiate-expr-2.cpp | 164 namespace N10 { namespace
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1713 SDValue N10 = N1.getOperand(0); in visitADD() local
1716 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) in visitADD()
1718 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), in visitADD()
3419 SDValue N10 = N1->getOperand(0); in MatchBSwapHWordLow() local
3420 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
3421 if (!N10.getNode()->hasOneUse()) in MatchBSwapHWordLow()
3423 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); in MatchBSwapHWordLow()
3426 N10 = N10.getOperand(0); in MatchBSwapHWordLow()
3430 if (N00 != N10) in MatchBSwapHWordLow()
3447 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16))) in MatchBSwapHWordLow()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1395 SDValue N10 = N1.getOperand(0); in visitADD() local
1398 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) in visitADD()
1400 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), in visitADD()
2557 SDValue N10 = N1->getOperand(0); in MatchBSwapHWordLow() local
2558 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { in MatchBSwapHWordLow()
2559 if (!N10.getNode()->hasOneUse()) in MatchBSwapHWordLow()
2561 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); in MatchBSwapHWordLow()
2564 N10 = N10.getOperand(0); in MatchBSwapHWordLow()
2568 if (N00 != N10) in MatchBSwapHWordLow()
2576 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) in MatchBSwapHWordLow()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8064 SDValue N10 = N1->getOperand(0); in performConcatVectorsCombine() local
8067 if (N00VT == N10.getValueType() && in performConcatVectorsCombine()
8078 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28189 SDValue N10 = N1.getOperand(0); in convertIntLogicToFPLogic() local
28191 EVT N10Type = N10.getValueType(); in convertIntLogicToFPLogic()
28193 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10); in convertIntLogicToFPLogic()
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