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1 #ifndef __NVIF_CLASS_H__
2 #define __NVIF_CLASS_H__
3 
4 /* these class numbers are made up by us, and not nvidia-assigned */
5 #define NVIF_CLASS_CONTROL                                    /* if0001.h */ -1
6 #define NVIF_CLASS_PERFMON                                    /* if0002.h */ -2
7 #define NVIF_CLASS_PERFDOM                                    /* if0003.h */ -3
8 #define NVIF_CLASS_SW_NV04                                    /* if0004.h */ -4
9 #define NVIF_CLASS_SW_NV10                                    /* if0005.h */ -5
10 #define NVIF_CLASS_SW_NV50                                    /* if0005.h */ -6
11 #define NVIF_CLASS_SW_GF100                                   /* if0005.h */ -7
12 
13 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
14 #define NV_DEVICE                                     /* cl0080.h */ 0x00000080
15 
16 #define NV_DMA_FROM_MEMORY                            /* cl0002.h */ 0x00000002
17 #define NV_DMA_TO_MEMORY                              /* cl0002.h */ 0x00000003
18 #define NV_DMA_IN_MEMORY                              /* cl0002.h */ 0x0000003d
19 
20 #define FERMI_TWOD_A                                                 0x0000902d
21 
22 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
23 
24 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
25 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
26 
27 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
28 
29 #define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
30 #define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
31 #define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
32 #define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
33 #define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
34 #define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
35 
36 #define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
37 #define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
38 #define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
39 #define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
40 #define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
41 
42 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
43 #define G82_DISP                                      /* cl5070.h */ 0x00008270
44 #define GT200_DISP                                    /* cl5070.h */ 0x00008370
45 #define GT214_DISP                                    /* cl5070.h */ 0x00008570
46 #define GT206_DISP                                    /* cl5070.h */ 0x00008870
47 #define GF110_DISP                                    /* cl5070.h */ 0x00009070
48 #define GK104_DISP                                    /* cl5070.h */ 0x00009170
49 #define GK110_DISP                                    /* cl5070.h */ 0x00009270
50 #define GM107_DISP                                    /* cl5070.h */ 0x00009470
51 #define GM204_DISP                                    /* cl5070.h */ 0x00009570
52 
53 #define NV31_MPEG                                                    0x00003174
54 #define G82_MPEG                                                     0x00008274
55 
56 #define NV74_VP2                                                     0x00007476
57 
58 #define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
59 #define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
60 #define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
61 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
62 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
63 
64 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
65 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
66 #define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
67 #define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
68 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
69 
70 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
71 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
72 #define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
73 #define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
74 #define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
75 #define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
76 #define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c
77 
78 #define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
79 #define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
80 #define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
81 #define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
82 #define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
83 #define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
84 #define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
85 #define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
86 #define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
87 #define GM204_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
88 
89 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
90 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
91 #define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
92 #define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
93 #define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
94 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
95 
96 #define FERMI_A                                       /* cl9097.h */ 0x00009097
97 #define FERMI_B                                       /* cl9097.h */ 0x00009197
98 #define FERMI_C                                       /* cl9097.h */ 0x00009297
99 
100 #define KEPLER_A                                      /* cl9097.h */ 0x0000a097
101 #define KEPLER_B                                      /* cl9097.h */ 0x0000a197
102 #define KEPLER_C                                      /* cl9097.h */ 0x0000a297
103 
104 #define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
105 #define MAXWELL_B                                     /* cl9097.h */ 0x0000b197
106 
107 #define NV74_BSP                                                     0x000074b0
108 
109 #define GT212_MSVLD                                                  0x000085b1
110 #define IGT21A_MSVLD                                                 0x000086b1
111 #define G98_MSVLD                                                    0x000088b1
112 #define GF100_MSVLD                                                  0x000090b1
113 #define GK104_MSVLD                                                  0x000095b1
114 
115 #define GT212_MSPDEC                                                 0x000085b2
116 #define G98_MSPDEC                                                   0x000088b2
117 #define GF100_MSPDEC                                                 0x000090b2
118 #define GK104_MSPDEC                                                 0x000095b2
119 
120 #define GT212_MSPPP                                                  0x000085b3
121 #define G98_MSPPP                                                    0x000088b3
122 #define GF100_MSPPP                                                  0x000090b3
123 
124 #define G98_SEC                                                      0x000088b4
125 
126 #define GT212_DMA                                                    0x000085b5
127 #define FERMI_DMA                                                    0x000090b5
128 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
129 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
130 
131 #define FERMI_DECOMPRESS                                             0x000090b8
132 
133 #define FERMI_COMPUTE_A                                              0x000090c0
134 #define FERMI_COMPUTE_B                                              0x000091c0
135 #define KEPLER_COMPUTE_A                                             0x0000a0c0
136 #define KEPLER_COMPUTE_B                                             0x0000a1c0
137 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
138 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
139 
140 #define NV74_CIPHER                                                  0x000074c1
141 #endif
142