Searched refs:NewSrc (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 934 TargetInstrInfo::RegSubRegPair NewSrc = in RewriteSource() local
944 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in RewriteSource()
958 MRI.clearKillFlags(NewSrc.Reg); in RewriteSource()
1213 TargetInstrInfo::RegSubRegPair NewSrc = CpyRewriter->getNewSource( in optimizeCoalescableCopy() local
1215 if (SrcReg == NewSrc.Reg || NewSrc.Reg == 0) in optimizeCoalescableCopy()
1219 if (CpyRewriter->RewriteCurrentSource(NewSrc.Reg, NewSrc.SubReg)) { in optimizeCoalescableCopy()
1221 MRI->clearKillFlags(NewSrc.Reg); in optimizeCoalescableCopy()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInst.cpp | 465 Variable *NewSrc = Func->makeVariable(Dest->getType()); in lower() local
467 NewSrc->setName(Func, Dest->getName() + "_phi"); in lower()
468 if (auto *NewSrc64On32 = llvm::dyn_cast<Variable64On32>(NewSrc)) in lower()
470 this->Dest = NewSrc; in lower()
471 return InstAssign::create(Func, Dest, NewSrc); in lower()
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| D | IceInstX86BaseImpl.h | 2244 const Operand *NewSrc = Src; in emit() local
2250 NewSrc = SrcVar->asType(Func, DestTy, NewRegNum); in emit()
2252 NewSrc->emit(Func); in emit()
2776 const Variable *NewSrc = Src1Var->asType(Func, IceType_i32, NewRegNum); in emit() local
2777 NewSrc->emit(Func); in emit()
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| D | IceTargetLoweringARM32.cpp | 3532 Operand *NewSrc; in lowerAssign() local
3537 NewSrc = legalize(Src0, Legal_Reg | Legal_Flex, Dest->getRegNum()); in lowerAssign()
3542 NewSrc = legalize(Src0, Legal_Reg); in lowerAssign()
3546 NewSrc = legalize(NewSrc, Legal_Reg | Legal_Mem); in lowerAssign()
3548 _mov(Dest, NewSrc); in lowerAssign()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 231 unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
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| D | X86InstrInfo.cpp | 2566 unsigned Opc, bool AllowSP, unsigned &NewSrc, in classifyLEAReg() argument
2582 NewSrc = SrcReg; in classifyLEAReg()
2586 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && in classifyLEAReg()
2587 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) in classifyLEAReg()
2599 NewSrc = getX86SubSuperRegister(Src.getReg(), 64); in classifyLEAReg()
2601 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); in classifyLEAReg()
2621 NewSrc = MF.getRegInfo().createVirtualRegister(RC); in classifyLEAReg()
2623 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) in classifyLEAReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1306 SDValue NewSrc = in SplitVecRes_ExtendOp() local
1309 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl); in SplitVecRes_ExtendOp()
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