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Searched refs:OP_SHR (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_target_gm107.cpp227 case OP_SHR: in getLatency()
Dnv50_ir_target_nvc0.cpp121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
608 case OP_SHR: in getThroughput()
Dnv50_ir_peephole.cpp629 case OP_SHR: in expr()
976 i->op = OP_SHR; in opnd()
1087 i->op = OP_SHR; in opnd()
1111 bld.mkOp2(OP_SHR, TYPE_U32, tA, tB, bld.mkImm(r)); in opnd()
1117 bld.mkOp2(OP_SHR, TYPE_U32, i->getDef(0), tB, bld.mkImm(s)); in opnd()
1141 bld.mkOp2(OP_SHR, TYPE_S32, tB, tA, bld.mkImm(l - 1)); in opnd()
1254 src->op == OP_SHR && in opnd()
1295 case OP_SHR: in opnd()
1991 if (shift && shift->op == OP_SHR && in handleCVT_EXTBF()
2002 } else if (insn->op == OP_SHR && in handleCVT_EXTBF()
Dnv50_ir_lowering_gm107.cpp224 bld.mkOp2(OP_SHR , TYPE_U32, tmp1, tmp0, bld.mkImm(16)); in handlePFETCH()
Dnv50_ir_target_nv50.cpp98 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
Dnv50_ir_lowering_nv50.cpp122 i[8] = bld->mkOp2(OP_SHR, fTy, r[0], t[1], bld->mkImm(halfSize * 8)); in expandIntegerMUL()
1197 bld.mkOp2(OP_SHR, TYPE_U32, def, def, bld.mkImm(16)); in handleRDSV()
1199 bld.mkOp2(OP_SHR, TYPE_U32, def, tid, bld.mkImm(26)); in handleRDSV()
Dnv50_ir_emit_nv50.cpp1584 code[1] = (i->op == OP_SHR) ? 0xe4000000 : 0xc4000000; in emitShift()
1585 if (i->op == OP_SHR && isSignedType(i->sType)) in emitShift()
1925 case OP_SHR: in emitInstruction()
Dnv50_ir.h68 OP_SHR, enumerator
Dnv50_ir_emit_gk110.cpp926 if (i->op == OP_SHR) { in emitShift()
2470 case OP_SHR: in emitInstruction()
Dnv50_ir_emit_nvc0.cpp949 if (i->op == OP_SHR) { in emitShift()
2665 case OP_SHR: in emitInstruction()
Dnv50_ir_emit_gm107.cpp3173 case OP_SHR: in emitInstruction()
Dnv50_ir_lowering_nvc0.cpp1845 bld.mkOp2(OP_SHR, TYPE_U32, off, bf, bld.mkImm(8)); in processSurfaceCoordsNVE4()