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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp54 SDValue LegalizeOp(SDValue Op);
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
60 SDValue UnrollVSETCC(SDValue Op);
66 SDValue Expand(SDValue Op);
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
76 SDValue ExpandSEXTINREG(SDValue Op);
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
99 SDValue ExpandBSWAP(SDValue Op);
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/external/llvm/include/llvm/CodeGen/
DMachineOperand.h589 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
590 Op.setImm(Val); in CreateImm()
591 return Op; in CreateImm()
595 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
596 Op.Contents.CI = CI; in CreateCImm()
597 return Op; in CreateCImm()
601 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
602 Op.Contents.CFP = CFP; in CreateFPImm()
603 return Op; in CreateFPImm()
615 MachineOperand Op(MachineOperand::MO_Register);
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DMachineRegisterInfo.h834 MachineOperand *Op; variable
835 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
848 assert(Op && "Cannot increment end iterator!"); in advance()
849 Op = getNextOperandForReg(Op); in advance()
853 if (Op) { in advance()
854 if (Op->isUse()) in advance()
855 Op = nullptr; in advance()
857 assert(!Op->isDebug() && "Can't have debug defs"); in advance()
861 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
862 (SkipDebug && Op->isDebug()))) in advance()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp54 SDValue LegalizeOp(SDValue Op);
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58 SDValue UnrollVSETCC(SDValue Op);
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
66 SDValue ExpandVSELECT(SDValue Op);
67 SDValue ExpandFNEG(SDValue Op);
71 SDValue PromoteVectorOp(SDValue Op);
104 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { in TranslateLegalizeResults() argument
106 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) in TranslateLegalizeResults()
107 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); in TranslateLegalizeResults()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineOperand.h472 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
473 Op.setImm(Val); in CreateImm()
474 return Op; in CreateImm()
478 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
479 Op.Contents.CI = CI; in CreateCImm()
480 return Op; in CreateCImm()
484 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
485 Op.Contents.CFP = CFP; in CreateFPImm()
486 return Op; in CreateFPImm()
495 MachineOperand Op(MachineOperand::MO_Register);
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DMachineRegisterInfo.h348 MachineOperand *Op; variable
349 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
366 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} in defusechain_iterator()
367 defusechain_iterator() : Op(0) {} in defusechain_iterator()
370 return Op == x.Op;
377 bool atEnd() const { return Op == 0; } in atEnd()
381 assert(Op && "Cannot increment end iterator!");
382 Op = Op->getNextOperandForReg();
385 while (Op && ((!ReturnUses && Op->isUse()) ||
386 (!ReturnDefs && Op->isDef()) ||
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/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp54 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
56 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
94 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
96 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
110 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
125 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
126 if (Op.isImm()) in printPCRelImm()
127 O << formatImm(Op.getImm()); in printPCRelImm()
129 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
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DX86ATTInstPrinter.cpp72 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
74 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
112 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
114 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
128 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
144 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
145 if (Op.isImm()) in printPCRelImm()
146 O << formatImm(Op.getImm()); in printPCRelImm()
148 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp360 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
362 switch(Op.getOpcode()) { in LowerOperation()
363 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
364 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); in LowerOperation()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.cpp59 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
61 switch (MI->getOperand(Op).getImm()) { in printSSECC()
80 const MCOperand &Op = MI->getOperand(OpNo); in print_pcrel_imm() local
81 if (Op.isImm()) in print_pcrel_imm()
83 O << (int)Op.getImm(); in print_pcrel_imm()
85 assert(Op.isExpr() && "unknown pcrel immediate operand"); in print_pcrel_imm()
86 O << *Op.getExpr(); in print_pcrel_imm()
92 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
93 if (Op.isReg()) { in printOperand()
94 O << '%' << getRegisterName(Op.getReg()); in printOperand()
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DX86IntelInstPrinter.cpp49 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, in printSSECC() argument
51 switch (MI->getOperand(Op).getImm()) { in printSSECC()
68 const MCOperand &Op = MI->getOperand(OpNo); in print_pcrel_imm() local
69 if (Op.isImm()) in print_pcrel_imm()
70 O << Op.getImm(); in print_pcrel_imm()
72 assert(Op.isExpr() && "unknown pcrel immediate operand"); in print_pcrel_imm()
73 O << *Op.getExpr(); in print_pcrel_imm()
84 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
85 if (Op.isReg()) { in printOperand()
86 PrintRegName(O, getRegisterName(Op.getReg())); in printOperand()
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/external/spirv-llvm/lib/SPIRV/libSPIRV/
DSPIRVOpCode.h51 SPIRVMap<Op, std::string>::init() { in init()
52 #define _SPIRV_OP(x, ...) add(Op##x, #x); in init()
56 SPIRV_DEF_NAMEMAP(Op, OpCodeNameMap) in SPIRV_DEF_NAMEMAP() argument
58 inline bool isAtomicOpCode(Op OpCode) { in SPIRV_DEF_NAMEMAP()
65 inline bool isBinaryOpCode(Op OpCode) { in isBinaryOpCode()
71 inline bool isShiftOpCode(Op OpCode) { in isShiftOpCode()
76 inline bool isLogicalOpCode(Op OpCode) { in isLogicalOpCode()
81 inline bool isBitwiseOpCode(Op OpCode) { in isBitwiseOpCode()
86 inline bool isBinaryShiftLogicalBitwiseOpCode(Op OpCode) { in isBinaryShiftLogicalBitwiseOpCode()
92 inline bool isCmpOpCode(Op OpCode) { in isCmpOpCode()
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/external/llvm/include/llvm/MC/
DMCInst.h112 MCOperand Op; in createReg() local
113 Op.Kind = kRegister; in createReg()
114 Op.RegVal = Reg; in createReg()
115 return Op; in createReg()
118 MCOperand Op; in createImm() local
119 Op.Kind = kImmediate; in createImm()
120 Op.ImmVal = Val; in createImm()
121 return Op; in createImm()
124 MCOperand Op; in createFPImm() local
125 Op.Kind = kFPImmediate; in createFPImm()
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/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInst.h98 MCOperand Op; in CreateReg() local
99 Op.Kind = kRegister; in CreateReg()
100 Op.RegVal = Reg; in CreateReg()
101 return Op; in CreateReg()
104 MCOperand Op; in CreateImm() local
105 Op.Kind = kImmediate; in CreateImm()
106 Op.ImmVal = Val; in CreateImm()
107 return Op; in CreateImm()
110 MCOperand Op; in CreateFPImm() local
111 Op.Kind = kFPImmediate; in CreateFPImm()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.h558 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
579 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
596 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
605 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
628 virtual void LowerAsmOperandForConstraint(SDValue Op,
717 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
788 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
793 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
794 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
795 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
DMBlazeAsmParser.cpp222 MBlazeOperand *Op = new MBlazeOperand(Token); in CreateToken() local
223 Op->Tok.Data = Str.data(); in CreateToken()
224 Op->Tok.Length = Str.size(); in CreateToken()
225 Op->StartLoc = S; in CreateToken()
226 Op->EndLoc = S; in CreateToken()
227 return Op; in CreateToken()
231 MBlazeOperand *Op = new MBlazeOperand(Register); in CreateReg() local
232 Op->Reg.RegNum = RegNum; in CreateReg()
233 Op->StartLoc = S; in CreateReg()
234 Op->EndLoc = E; in CreateReg()
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h35 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
44 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h34 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
66 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
67 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
68 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
71 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
77 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
78 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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/external/clang/lib/CodeGen/
DCGExprComplex.cpp150 ComplexPairTy EmitCast(CastKind CK, Expr *Op, QualType DestTy);
235 ComplexPairTy EmitBinAdd(const BinOpInfo &Op);
236 ComplexPairTy EmitBinSub(const BinOpInfo &Op);
237 ComplexPairTy EmitBinMul(const BinOpInfo &Op);
238 ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
241 const BinOpInfo &Op);
423 ComplexPairTy ComplexExprEmitter::EmitCast(CastKind CK, Expr *Op, in EmitCast() argument
435 return Visit(Op); in EmitCast()
438 LValue origLV = CGF.EmitLValue(Op); in EmitCast()
441 return EmitLoadOfLValue(CGF.MakeAddrLValue(V, DestTy), Op->getExprLoc()); in EmitCast()
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/external/llvm/lib/Bitcode/Reader/
DBitstreamReader.cpp55 const BitCodeAbbrevOp &Op) { in readAbbreviatedField() argument
56 assert(!Op.isLiteral() && "Not to be used with literals!"); in readAbbreviatedField()
59 switch (Op.getEncoding()) { in readAbbreviatedField()
64 assert((unsigned)Op.getEncodingData() <= Cursor.MaxChunkSize); in readAbbreviatedField()
65 return Cursor.Read((unsigned)Op.getEncodingData()); in readAbbreviatedField()
67 assert((unsigned)Op.getEncodingData() <= Cursor.MaxChunkSize); in readAbbreviatedField()
68 return Cursor.ReadVBR64((unsigned)Op.getEncodingData()); in readAbbreviatedField()
76 const BitCodeAbbrevOp &Op) { in skipAbbreviatedField() argument
77 assert(!Op.isLiteral() && "Not to be used with literals!"); in skipAbbreviatedField()
80 switch (Op.getEncoding()) { in skipAbbreviatedField()
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
169 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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/external/eigen/unsupported/Eigen/CXX11/src/Tensor/
DTensorReduction.h24 template<typename Op, typename Dims, typename XprType,template <class> class MakePointer_ >
25 struct traits<TensorReductionOp<Op, Dims, XprType, MakePointer_> >
43 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
44 struct eval<TensorReductionOp<Op, Dims, XprType, MakePointer_>, Eigen::Dense>
46 typedef const TensorReductionOp<Op, Dims, XprType, MakePointer_>& type;
49 template<typename Op, typename Dims, typename XprType, template <class> class MakePointer_>
50 struct nested<TensorReductionOp<Op, Dims, XprType, MakePointer_>, 1, typename eval<TensorReductionO…
52 typedef TensorReductionOp<Op, Dims, XprType, MakePointer_> type;
129 template <int DimIndex, typename Self, typename Op>
131 …RONG_INLINE void reduce(const Self& self, typename Self::Index firstIndex, Op& reducer, typename S…
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/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h411 void LowerAsmOperandForConstraint(SDValue Op,
458 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
493 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
494 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
495 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
508 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
509 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
510 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
511 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
512 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
342 auto Op = make_unique<SparcOperand>(k_Token); in CreateToken() local
343 Op->Tok.Data = Str.data(); in CreateToken()
344 Op->Tok.Length = Str.size(); in CreateToken()
345 Op->StartLoc = S; in CreateToken()
346 Op->EndLoc = S; in CreateToken()
347 return Op; in CreateToken()
352 auto Op = make_unique<SparcOperand>(k_Register); in CreateReg() local
353 Op->Reg.RegNum = RegNum; in CreateReg()
354 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; in CreateReg()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h235 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
248 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
277 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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