Searched refs:OpR (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | InstrInfoEmitter.cpp | 73 Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef(); in GetOperandInfo() local
74 OperandList.back().Rec = OpR; in GetOperandInfo()
79 Record *OpR = OperandList[j].Rec; in GetOperandInfo() local
82 if (OpR->isSubClassOf("RegisterOperand")) in GetOperandInfo()
83 OpR = OpR->getValueAsDef("RegClass"); in GetOperandInfo()
84 if (OpR->isSubClassOf("RegisterClass")) in GetOperandInfo()
85 Res += getQualifiedName(OpR) + "RegClassID, "; in GetOperandInfo()
86 else if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
87 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; in GetOperandInfo()
96 if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
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| /external/llvm/utils/TableGen/ |
| D | InstrInfoEmitter.cpp | 109 Record *OpR = cast<DefInit>(MIOI->getArg(j))->getDef(); in GetOperandInfo() local
110 OperandList.back().Rec = OpR; in GetOperandInfo()
115 Record *OpR = OperandList[j].Rec; in GetOperandInfo() local
118 if (OpR->isSubClassOf("RegisterOperand")) in GetOperandInfo()
119 OpR = OpR->getValueAsDef("RegClass"); in GetOperandInfo()
120 if (OpR->isSubClassOf("RegisterClass")) in GetOperandInfo()
121 Res += getQualifiedName(OpR) + "RegClassID, "; in GetOperandInfo()
122 else if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
123 Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; in GetOperandInfo()
132 if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 1199 const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1; in isLegalToPacketizeTogether() local
1200 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) { in isLegalToPacketizeTogether()
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| /external/llvm/lib/Transforms/IPO/ |
| D | MergeFunctions.cpp | 1199 Value *OpR = InstR->getOperand(i); in cmpBasicBlocks() local
1200 if (int Res = cmpValues(OpL, OpR)) in cmpBasicBlocks()
1203 assert(cmpTypes(OpL->getType(), OpR->getType()) == 0); in cmpBasicBlocks()
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 1285 Value *OpL = nullptr, *OpR = nullptr;
1298 auto RHS = m_LShr(m_Neg(m_Value(OpR)), m_SpecificInt(ShiftWidth));
1301 return Signum.match(V) && OpL == OpR && Val.match(OpL);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 952 SDValue OpR = GetPromotedInteger(NewRHS); in PromoteSetCCOperands() local
960 OpR->getOpcode() == ISD::AssertSext && in PromoteSetCCOperands()
961 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) { in PromoteSetCCOperands()
963 NewRHS = OpR; in PromoteSetCCOperands()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 2965 Operand *createShiftedOperand(Cfg *Func, Variable *OpR) const { in createShiftedOperand()
2966 assert(OpR->mustHaveReg()); in createShiftedOperand()
2968 return OpR; in createShiftedOperand()
2971 Func, IceType_i32, OpR, OperandARM32::LSL, in createShiftedOperand()
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