| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 75 unsigned Opc1, Opc2; in processBlock() local
82 Opc1 = PPC::ADDItlsgdL; in processBlock()
86 Opc1 = PPC::ADDItlsldL; in processBlock()
90 Opc1 = PPC::ADDItlsgdL32; in processBlock()
94 Opc1 = PPC::ADDItlsldL32; in processBlock()
105 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3) in processBlock()
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| D | PPCISelDAGToDAG.cpp | 3058 unsigned Opc1, Opc2, Opc3; in Select() local
3062 Opc1 = PPC::VSPLTISB; in Select()
3067 Opc1 = PPC::VSPLTISH; in Select()
3073 Opc1 = PPC::VSPLTISW; in Select()
3087 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3100 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3102 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3115 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
3117 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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| D | Mips16ISelLowering.cpp | 584 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, in emitSelT16() argument
622 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
649 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
688 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 55 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
58 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
100 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
103 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
106 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
124 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1) in areLoadsFromSameBasePtr()
132 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
157 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
167 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
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| /external/swiftshader/third_party/LLVM/include/llvm/Support/ |
| D | PatternMatch.h | 401 template<typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2>
410 if (V->getValueID() == Value::InstructionVal + Opc1 || in match()
416 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && in match()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 1831 unsigned Opc1 = Lane >> 2; in emitNEONLaneInstruction() local
1833 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); in emitNEONLaneInstruction()
1834 Binary |= (Opc1 << 21); in emitNEONLaneInstruction()
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| /external/llvm/include/llvm/IR/ |
| D | PatternMatch.h | 635 template <typename LHS_t, typename RHS_t, unsigned Opc1, unsigned Opc2>
643 if (V->getValueID() == Value::InstructionVal + Opc1 || in match()
649 return (CE->getOpcode() == Opc1 || CE->getOpcode() == Opc2) && in match()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 3136 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
3138 switch (Opc1) { in areLoadsFromSameBasePtr()
3244 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
3246 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
3249 switch (Opc1) { in shouldScheduleLoadsNear()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 6614 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
6616 switch (Opc1) { in areLoadsFromSameBasePtr()
6722 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
6724 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
6727 switch (Opc1) { in shouldScheduleLoadsNear()
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| D | X86ISelLowering.cpp | 17382 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17400 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17432 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0; in LowerINTRINSIC_WO_CHAIN()
17457 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17543 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17611 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
17717 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
17721 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
17750 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
17754 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| D | X86IntrinsicsInfo.h | 46 uint16_t Opc1; member
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 4036 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
4063 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 375 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
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