| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 413 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n"); in TEST()
414 COMPARE_BOTH(Orn(r0, r0, 0xffffffff), ""); in TEST()
420 COMPARE_A32(Orn(r0, r1, 1), in TEST()
429 COMPARE_BOTH(Orn(r0, r1, 0x00ffffff), "orr r0, r1, #0xff000000\n"); in TEST()
430 COMPARE_BOTH(Orn(r0, r1, 0xff00ffff), "orr r0, r1, #0xff0000\n"); in TEST()
438 COMPARE_T32(Orn(r0, r1, 0xabcd2345), in TEST()
447 COMPARE_A32(Orn(r0, r1, r2), in TEST()
451 COMPARE_A32(Orn(r0, r0, r1), in TEST()
455 COMPARE_A32(Orn(r0, r1, r0), in TEST()
459 COMPARE_A32(Orn(r0, r0, r0), in TEST()
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 128 M(Orn) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 128 M(Orn) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 128 M(Orn) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 128 M(Orn) \
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| D | test-assembler-aarch32.cc | 3175 __ Orn(r0, r0, 0xffffffff); in TEST() local
3219 __ Orn(r4, r0, 0); in TEST() local
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 694 __ Orn(x2, x0, Operand(x1)); in TEST() local
695 __ Orn(w3, w0, Operand(w1, LSL, 4)); in TEST() local
696 __ Orn(x4, x0, Operand(x1, LSL, 4)); in TEST() local
697 __ Orn(x5, x0, Operand(x1, LSR, 1)); in TEST() local
698 __ Orn(w6, w0, Operand(w1, ASR, 1)); in TEST() local
699 __ Orn(x7, x0, Operand(x1, ASR, 1)); in TEST() local
700 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST() local
701 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST() local
702 __ Orn(w10, w0, 0x0000ffff); in TEST() local
703 __ Orn(x11, x0, 0x0000ffff0000ffff); in TEST() local
[all …]
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| D | test-disasm-aarch64.cc | 2979 COMPARE_MACRO(Orn(w8, w9, 0), "mov w8, #0xffffffff"); in TEST()
2980 COMPARE_MACRO(Orn(x8, x9, 0), "mov x8, #0xffffffffffffffff"); in TEST()
2997 COMPARE_MACRO(Orn(w20, w21, 0xffffffff), "mov w20, w21"); in TEST()
2998 COMPARE_MACRO(Orn(x20, x21, 0xffffffff), "orr x20, x21, #0xffffffff00000000"); in TEST()
2999 COMPARE_MACRO(Orn(x20, x21, 0xffffffffffffffff), "mov x20, x21"); in TEST()
4509 COMPARE_MACRO(Orn(v6.V8B(), v7.V8B(), v8.V8B()), "orn v6.8b, v7.8b, v8.8b"); in TEST()
4510 COMPARE_MACRO(Orn(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1079 __ Orn(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1083 __ Orn(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 98 void MacroAssembler::Orn(const Register& rd, in Orn() function
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| D | macro-assembler-arm64.h | 189 inline void Orn(const Register& rd,
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 619 void Orn(const Register& rd, const Register& rn, const Operand& operand);
2158 V(orn, Orn) \
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| D | macro-assembler-aarch64.cc | 736 void MacroAssembler::Orn(const Register& rd, in Orn() function in vixl::aarch64::MacroAssembler
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2744 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { in Orn() function
2764 void Orn(Register rd, Register rn, const Operand& operand) { in Orn() function
2765 Orn(al, rd, rn, operand); in Orn()
2767 void Orn(FlagsUpdate flags, in Orn() function
2774 Orn(cond, rd, rn, operand); in Orn()
2780 Orn(cond, rd, rn, operand); in Orn()
2784 void Orn(FlagsUpdate flags, in Orn() function
2788 Orn(flags, al, rd, rn, operand); in Orn()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 44 # Vector And, Orr, Eor, Orn, Bic
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