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Searched refs:PCB (Results 1 – 11 of 11) sorted by relevance

/external/libese/libese-teq1/
Dteq1.c120 teq1_trace_transmit(frame->header.PCB, frame->header.LEN); in teq1_transmit()
165 teq1_trace_receive(frame->header.PCB, frame->header.LEN); in teq1_receive()
185 switch (bs_get(PCB.type, frame->header.PCB)) { in teq1_fill_info_block()
209 bs_assign(&frame->header.PCB, PCB.I.more_data, 0); in teq1_fill_info_block()
211 frame->header.PCB |= bs_mask(PCB.I.more_data, 1); in teq1_fill_info_block()
224 switch (bs_get(PCB.type, frame->header.PCB)) { in teq1_get_app_data()
255 if (rx_frame->header.PCB == 255) { in teq1_frame_error_check()
267 switch (bs_get(PCB.type, tx_frame->header.PCB)) { in teq1_frame_error_check()
270 chained = bs_get(PCB.I.more_data, tx_frame->header.PCB); in teq1_frame_error_check()
272 bs_get(PCB.I.send_seq, tx_frame->header.PCB); in teq1_frame_error_check()
[all …]
/external/libese/libese-teq1/tests/
Dteq1_unittests.cpp66 tx_frame_.header.PCB = TEQ1_I(0, 0); in TEST_F()
70 rx_frame_.header.PCB = *pcb; in TEST_F()
75 …teq1_frame_error_check(&state_, &tx_frame_, &rx_frame_)) << teq1_pcb_to_name(rx_frame_.header.PCB); in TEST_F()
133 tx_frame_.header.PCB = TEQ1_I(0, 0); in SetUp()
138 rx_frame_.header.PCB = TEQ1_I(0, 0); in SetUp()
148 teq1_trace_transmit(tx_frame_.header.PCB, tx_frame_.header.LEN); in RunRules()
149 teq1_trace_receive(rx_frame_.header.PCB, rx_frame_.header.LEN); in RunRules()
155 EXPECT_EQ(0, tx_next_.header.PCB) in RunRules()
156 << "Actual next TX: " << teq1_pcb_to_name(tx_next_.header.PCB); in RunRules()
182 tx_frame_.header.PCB = TEQ1_I(1, 0); in TEST_F()
[all …]
/external/libese/libese-teq1/include/ese/
Dteq1.h73 const static struct PcbSpec PCB = { variable
96 uint8_t PCB; member
198 #define teq1_trace_transmit(PCB, LEN) ALOGI("%-20s --> %20s [%3hhu]", teq1_pcb_to_name(PCB), "", LE… argument
199 #define teq1_trace_receive(PCB, LEN) ALOGI("%-20s <-- %20s [%3hhu]", "", teq1_pcb_to_name(PCB), LEN) argument
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.td29 def PCB : MSP430Reg<0, "r0">;
49 def PC : MSP430RegWithSubregs<0, "r0", [PCB]>;
73 PCB, SPB, SRB, CGB)>;
DMSP430RegisterInfo.cpp79 Reserved.set(MSP430::PCB); in getReservedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430RegisterInfo.td29 def PCB : MSP430Reg<0, "r0">;
49 def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
73 PCB, SPB, SRB, CGB)>;
DMSP430RegisterInfo.cpp82 Reserved.set(MSP430::PCB); in getReservedRegs()
/external/syslinux/core/lwip/doc/
Drawapi.txt101 identifier (i.e., a protocol control block - PCB) is created with the
102 tcp_new() function. This PCB can then be either set to listen for new
107 Creates a new connection identifier (PCB). If memory is not
403 Clears the UDP PCB list.
407 Clears the TCP PCB list and clears some internal TCP timers.
/external/walt/arduino/walt/
Dwalt.ino60 #define DEBUG_LED1 11 // On r0.7 PCB: D4 - Red
61 #define DEBUG_LED2 12 // On r0.7 PCB: D3 - Green
/external/walt/docs/usage/
DWALT_usage.md15 * Assembled WALT PCB and base, with DIP socket for Teensy LC
/external/syslinux/core/lwip/
DCHANGELOG721 algorithm at PCB level
2054 * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match