1 #ifndef _GPXE_PCI_H
2 #define _GPXE_PCI_H
3
4 /*
5 * Support for NE2000 PCI clones added David Monro June 1997
6 * Generalised for other PCI NICs by Ken Yap July 1997
7 * PCI support rewritten by Michael Brown 2006
8 *
9 * Most of this is taken from /usr/src/linux/include/linux/pci.h.
10 */
11
12 /*
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2, or (at
16 * your option) any later version.
17 */
18
19 FILE_LICENCE ( GPL2_ONLY );
20
21 #include <stdint.h>
22 #include <gpxe/device.h>
23 #include <gpxe/tables.h>
24 #include <gpxe/pci_io.h>
25 #include "pci_ids.h"
26
27 /*
28 * PCI constants
29 *
30 */
31
32 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
33 #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */
34 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
35
36 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
37 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
38
39 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
40 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
41 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
42 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
43 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
44 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
45 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
46 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
47
48
49 #define PCI_VENDOR_ID 0x00 /* 16 bits */
50 #define PCI_DEVICE_ID 0x02 /* 16 bits */
51 #define PCI_COMMAND 0x04 /* 16 bits */
52
53 #define PCI_STATUS 0x06 /* 16 bits */
54 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
55 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
56 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
57 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
58 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
59 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
60 #define PCI_STATUS_DEVSEL_FAST 0x000
61 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
62 #define PCI_STATUS_DEVSEL_SLOW 0x400
63 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
64 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
65 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
66 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
67 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
68
69 #define PCI_REVISION 0x08 /* 8 bits */
70 #define PCI_REVISION_ID 0x08 /* 8 bits */
71 #define PCI_CLASS_REVISION 0x08 /* 32 bits */
72 #define PCI_CLASS_CODE 0x0b /* 8 bits */
73 #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
74 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
75 #define PCI_HEADER_TYPE_NORMAL 0
76 #define PCI_HEADER_TYPE_BRIDGE 1
77 #define PCI_HEADER_TYPE_CARDBUS 2
78
79
80 /* Header type 0 (normal devices) */
81 #define PCI_CARDBUS_CIS 0x28
82 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
83 #define PCI_SUBSYSTEM_ID 0x2e
84
85 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
86 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
87 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
88 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
89 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
90 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
91
92 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
93 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
94 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
95
96 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
97 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
98 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
99 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
100 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
101 #define PCI_BASE_ADDRESS_IO_MASK (~0x03)
102 #define PCI_ROM_ADDRESS 0x30 /* 32 bits */
103 #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM,
104 bits 31..11 are address,
105 10..2 are reserved */
106
107 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
108
109 #define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */
110 #define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */
111
112 /* Header type 1 (PCI-to-PCI bridges) */
113 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
114 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
115 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
116 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
117 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
118 #define PCI_IO_LIMIT 0x1d
119 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
120 #define PCI_IO_RANGE_TYPE_16 0x00
121 #define PCI_IO_RANGE_TYPE_32 0x01
122 #define PCI_IO_RANGE_MASK ~0x0f
123 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
124 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
125 #define PCI_MEMORY_LIMIT 0x22
126 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
127 #define PCI_MEMORY_RANGE_MASK ~0x0f
128 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
129 #define PCI_PREF_MEMORY_LIMIT 0x26
130 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
131 #define PCI_PREF_RANGE_TYPE_32 0x00
132 #define PCI_PREF_RANGE_TYPE_64 0x01
133 #define PCI_PREF_RANGE_MASK ~0x0f
134 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135 #define PCI_PREF_LIMIT_UPPER32 0x2c
136 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
137 #define PCI_IO_LIMIT_UPPER16 0x32
138 /* 0x34 same as for htype 0 */
139 /* 0x35-0x3b is reserved */
140 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
141 /* 0x3c-0x3d are same as for htype 0 */
142 #define PCI_BRIDGE_CONTROL 0x3e
143 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
144 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
145 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
146 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
147 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
148 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
149 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
150
151 #define PCI_CB_CAPABILITY_LIST 0x14
152
153 /* Capability lists */
154
155 #define PCI_CAP_LIST_ID 0 /* Capability ID */
156 #define PCI_CAP_ID_PM 0x01 /* Power Management */
157 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
158 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
159 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
160 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
161 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
162 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
163 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
164 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
165 #define PCI_CAP_SIZEOF 4
166
167 /* Power Management Registers */
168
169 #define PCI_PM_PMC 2 /* PM Capabilities Register */
170 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
171 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
172 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
173 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
174 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
175 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
176 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
177 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
178 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
179 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
180 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
181 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
182 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
183 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
184 #define PCI_PM_CTRL 4 /* PM control and status register */
185 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
186 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
187 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
188 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
189 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
190 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
191 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
192 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
193 #define PCI_PM_DATA_REGISTER 7 /* (??) */
194 #define PCI_PM_SIZEOF 8
195
196 /* AGP registers */
197
198 #define PCI_AGP_VERSION 2 /* BCD version number */
199 #define PCI_AGP_RFU 3 /* Rest of capability flags */
200 #define PCI_AGP_STATUS 4 /* Status register */
201 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
202 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
203 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
204 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
205 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
206 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
207 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
208 #define PCI_AGP_COMMAND 8 /* Control register */
209 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
210 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
211 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
212 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
213 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
214 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
215 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
216 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
217 #define PCI_AGP_SIZEOF 12
218
219 /* Slot Identification */
220
221 #define PCI_SID_ESR 2 /* Expansion Slot Register */
222 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
223 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
224 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
225
226 /* Message Signalled Interrupts registers */
227
228 #define PCI_MSI_FLAGS 2 /* Various flags */
229 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
230 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
231 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
232 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
233 #define PCI_MSI_RFU 3 /* Rest of capability flags */
234 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
235 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
236 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
237 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
238
239 /* Advanced Error Reporting */
240
241 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
242 #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
243 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
244 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
245 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
246 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
247 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
248 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
249 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
250 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
251 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
252 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
253 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
254 /* Same bits as above */
255 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
256 /* Same bits as above */
257 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
258 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
259 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
260 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
261 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
262 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
263 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
264 /* Same bits as above */
265
266 /** A PCI device ID list entry */
267 struct pci_device_id {
268 /** Name */
269 const char *name;
270 /** PCI vendor ID */
271 uint16_t vendor;
272 /** PCI device ID */
273 uint16_t device;
274 /** Arbitrary driver data */
275 unsigned long driver_data;
276 };
277
278 /** Match-anything ID */
279 #define PCI_ANY_ID 0xffff
280
281 /** A PCI device */
282 struct pci_device {
283 /** Generic device */
284 struct device dev;
285 /** Memory base
286 *
287 * This is the physical address of the first valid memory BAR.
288 */
289 unsigned long membase;
290 /**
291 * I/O address
292 *
293 * This is the physical address of the first valid I/O BAR.
294 */
295 unsigned long ioaddr;
296 /** Vendor ID */
297 uint16_t vendor;
298 /** Device ID */
299 uint16_t device;
300 /** Device class */
301 uint32_t class;
302 /** Interrupt number */
303 uint8_t irq;
304 /** Bus number */
305 uint8_t bus;
306 /** Device and function number */
307 uint8_t devfn;
308 /** Driver for this device */
309 struct pci_driver *driver;
310 /** Driver-private data
311 *
312 * Use pci_set_drvdata() and pci_get_drvdata() to access this
313 * field.
314 */
315 void *priv;
316 /** Driver name */
317 const char *driver_name;
318 };
319
320 /** A PCI driver */
321 struct pci_driver {
322 /** PCI ID table */
323 struct pci_device_id *ids;
324 /** Number of entries in PCI ID table */
325 unsigned int id_count;
326 /**
327 * Probe device
328 *
329 * @v pci PCI device
330 * @v id Matching entry in ID table
331 * @ret rc Return status code
332 */
333 int ( * probe ) ( struct pci_device *pci,
334 const struct pci_device_id *id );
335 /**
336 * Remove device
337 *
338 * @v pci PCI device
339 */
340 void ( * remove ) ( struct pci_device *pci );
341 };
342
343 /** PCI driver table */
344 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
345
346 /** Declare a PCI driver */
347 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
348
349 #define PCI_DEVFN( slot, func ) ( ( (slot) << 3 ) | (func) )
350 #define PCI_SLOT( devfn ) ( ( (devfn) >> 3 ) & 0x1f )
351 #define PCI_FUNC( devfn ) ( (devfn) & 0x07 )
352 #define PCI_BUS( busdevfn ) ( (busdevfn) >> 8 )
353 #define PCI_BUSDEVFN( bus, devfn ) ( ( (bus) << 8 ) | (devfn) )
354
355 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
356 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
357 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
358
359 /*
360 * PCI_ROM is used to build up entries in a struct pci_id array. It
361 * is also parsed by parserom.pl to generate Makefile rules and files
362 * for rom-o-matic.
363 *
364 * PCI_ID can be used to generate entries without creating a
365 * corresponding ROM in the build process.
366 */
367 #define PCI_ID( _vendor, _device, _name, _description, _data ) { \
368 .vendor = _vendor, \
369 .device = _device, \
370 .name = _name, \
371 .driver_data = _data \
372 }
373 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
374 PCI_ID( _vendor, _device, _name, _description, _data )
375
376 extern void adjust_pci_device ( struct pci_device *pci );
377 extern unsigned long pci_bar_start ( struct pci_device *pci,
378 unsigned int reg );
379 extern int pci_find_capability ( struct pci_device *pci, int capability );
380 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
381
382 /**
383 * Set PCI driver-private data
384 *
385 * @v pci PCI device
386 * @v priv Private data
387 */
pci_set_drvdata(struct pci_device * pci,void * priv)388 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
389 pci->priv = priv;
390 }
391
392 /**
393 * Get PCI driver-private data
394 *
395 * @v pci PCI device
396 * @ret priv Private data
397 */
pci_get_drvdata(struct pci_device * pci)398 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
399 return pci->priv;
400 }
401
402 #endif /* _GPXE_PCI_H */
403