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Searched refs:PTR (Results 1 – 25 of 160) sorted by relevance

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/external/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll34 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
35 ; MIPS32R6: lw $2, 0($[[PTR]])
43 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
44 ; MIPS64R6: lw $2, 0($[[PTR]])
60 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)(
61 ; MIPS32R6: sw $4, 0($[[PTR]])
69 ; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)(
70 ; MIPS64R6: sw $4, 0($[[PTR]])
90 ; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)(
91 ; MIPS32R6-DAG: lw $2, 0($[[PTR]])
[all …]
/external/python/cpython2/Modules/_ctypes/libffi_msvc/
Dwin64.asm20 mov QWORD PTR [rsp+8], rcx
23 movlpd QWORD PTR [rsp+8], xmm0
28 mov QWORD PTR [rsp+16], rdx
31 movlpd QWORD PTR [rsp+16], xmm1
36 mov QWORD PTR [rsp+24], r8
39 movlpd QWORD PTR [rsp+24], xmm2
44 mov QWORD PTR [rsp+32], r9
47 movlpd QWORD PTR [rsp+32], xmm3
77 mov QWORD PTR [rsp+32], r9
78 mov QWORD PTR [rsp+24], r8
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/x86/
Dwin64.S39 mov QWORD PTR [rsp+8], rcx
42 movlpd QWORD PTR [rsp+8], xmm0
47 mov QWORD PTR [rsp+16], rdx
50 movlpd QWORD PTR [rsp+16], xmm1
55 mov QWORD PTR [rsp+24], r8
58 movlpd QWORD PTR [rsp+24], xmm2
63 mov QWORD PTR [rsp+32], r9
66 movlpd QWORD PTR [rsp+32], xmm3
85 mov QWORD PTR [rsp+32], r9
86 mov QWORD PTR [rsp+24], r8
[all …]
/external/clang/include/clang/AST/
DEvaluatedExprVisitor.h35 #define PTR(CLASS) typename Ptr<CLASS>::type macro
41 void VisitDeclRefExpr(PTR(DeclRefExpr) E) { } in VisitDeclRefExpr()
42 void VisitOffsetOfExpr(PTR(OffsetOfExpr) E) { } in VisitOffsetOfExpr()
43 void VisitUnaryExprOrTypeTraitExpr(PTR(UnaryExprOrTypeTraitExpr) E) { } in VisitUnaryExprOrTypeTraitExpr()
44 void VisitExpressionTraitExpr(PTR(ExpressionTraitExpr) E) { } in VisitExpressionTraitExpr()
45 void VisitBlockExpr(PTR(BlockExpr) E) { } in VisitBlockExpr()
46 void VisitCXXUuidofExpr(PTR(CXXUuidofExpr) E) { } in VisitCXXUuidofExpr()
47 void VisitCXXNoexceptExpr(PTR(CXXNoexceptExpr) E) { } in VisitCXXNoexceptExpr()
49 void VisitMemberExpr(PTR(MemberExpr) E) { in VisitMemberExpr()
54 void VisitChooseExpr(PTR(ChooseExpr) E) { in VisitChooseExpr()
[all …]
DStmtVisitor.h36 #define PTR(CLASS) typename Ptr<CLASS>::type macro
38 return static_cast<ImplClass*>(this)->Visit ## NAME(static_cast<PTR(CLASS)>(S))
40 RetTy Visit(PTR(Stmt) S) { in Visit()
45 if (PTR(BinaryOperator) BinOp = dyn_cast<BinaryOperator>(S)) { in Visit()
82 } else if (PTR(UnaryOperator) UnOp = dyn_cast<UnaryOperator>(S)) { in Visit()
114 RetTy Visit ## CLASS(PTR(CLASS) S) { DISPATCH(PARENT, PARENT); }
120 RetTy VisitBin ## NAME(PTR(BinaryOperator) S) { \
140 RetTy VisitBin ## NAME(PTR(CompoundAssignOperator) S) { \ in BINOP_FALLBACK()
152 RetTy VisitUnary ## NAME(PTR(UnaryOperator) S) { \
166 RetTy VisitStmt(PTR(Stmt) Node) { return RetTy(); }
[all …]
/external/libvpx/libvpx/vp8/common/x86/
Dsubpixel_ssse3.asm48 movsxd rdx, DWORD PTR arg(5) ;table index
58 cmp esi, DWORD PTR [rax]
61 movdqa xmm4, XMMWORD PTR [rax] ;k0_k5
62 movdqa xmm5, XMMWORD PTR [rax+256] ;k2_k4
63 movdqa xmm6, XMMWORD PTR [rax+128] ;k1_k3
74 movq xmm0, MMWORD PTR [rsi - 2] ; -2 -1 0 1 2 3 4 5
76 movq xmm2, MMWORD PTR [rsi + 3] ; 3 4 5 6 7 8 9 10
117 movdqa xmm5, XMMWORD PTR [rax+256] ;k2_k4
118 movdqa xmm6, XMMWORD PTR [rax+128] ;k1_k3
120 movdqa xmm3, XMMWORD PTR [GLOBAL(shuf2bfrom1)]
[all …]
Dcopy_sse2.asm39 movdqu xmm0, XMMWORD PTR [rsi]
40 movdqu xmm1, XMMWORD PTR [rsi + 16]
41 movdqu xmm2, XMMWORD PTR [rsi + rax]
42 movdqu xmm3, XMMWORD PTR [rsi + rax + 16]
46 movdqu xmm4, XMMWORD PTR [rsi]
47 movdqu xmm5, XMMWORD PTR [rsi + 16]
48 movdqu xmm6, XMMWORD PTR [rsi + rax]
49 movdqu xmm7, XMMWORD PTR [rsi + rax + 16]
53 movdqa XMMWORD PTR [rdi], xmm0
54 movdqa XMMWORD PTR [rdi + 16], xmm1
[all …]
Dcopy_sse3.asm101 movdqu xmm0, XMMWORD PTR [src_ptr]
102 movdqu xmm1, XMMWORD PTR [src_ptr + 16]
103 movdqu xmm2, XMMWORD PTR [src_ptr + src_stride]
104 movdqu xmm3, XMMWORD PTR [src_ptr + src_stride + 16]
105 movdqu xmm4, XMMWORD PTR [end_ptr]
106 movdqu xmm5, XMMWORD PTR [end_ptr + 16]
107 movdqu xmm6, XMMWORD PTR [end_ptr + src_stride]
108 movdqu xmm7, XMMWORD PTR [end_ptr + src_stride + 16]
114 movdqa XMMWORD PTR [ref_ptr], xmm0
115 movdqa XMMWORD PTR [ref_ptr + 16], xmm1
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dsad_sse3.asm84 movdqa xmm0, XMMWORD PTR [%2]
85 lddqu xmm5, XMMWORD PTR [%3]
86 lddqu xmm6, XMMWORD PTR [%3+1]
87 lddqu xmm7, XMMWORD PTR [%3+2]
93 movdqa xmm0, XMMWORD PTR [%2]
94 lddqu xmm1, XMMWORD PTR [%3]
95 lddqu xmm2, XMMWORD PTR [%3+1]
96 lddqu xmm3, XMMWORD PTR [%3+2]
106 movdqa xmm0, XMMWORD PTR [%2+%4]
107 lddqu xmm1, XMMWORD PTR [%3+%5]
[all …]
Dsad_sse4.asm16 movdqa xmm0, XMMWORD PTR [rsi]
17 movq xmm1, MMWORD PTR [rdi]
18 movq xmm3, MMWORD PTR [rdi+8]
19 movq xmm2, MMWORD PTR [rdi+16]
37 movdqa xmm0, XMMWORD PTR [rsi]
38 movq xmm5, MMWORD PTR [rdi]
39 movq xmm3, MMWORD PTR [rdi+8]
40 movq xmm2, MMWORD PTR [rdi+16]
60 movdqa xmm0, XMMWORD PTR [rsi + rax]
61 movq xmm5, MMWORD PTR [rdi+ rdx]
[all …]
Dhighbd_variance_impl_sse2.asm37 movsxd rax, DWORD PTR arg(1) ;[source_stride]
38 movsxd rdx, DWORD PTR arg(3) ;[recon_stride]
70 movdqu xmm1, XMMWORD PTR [rsi]
71 movdqu xmm2, XMMWORD PTR [rdi]
87 movdqu xmm3, XMMWORD PTR [rsi+16]
90 movdqu xmm2, XMMWORD PTR [rdi+16]
94 movdqu xmm1, XMMWORD PTR [rsi+rax]
97 movdqu xmm2, XMMWORD PTR [rdi+rdx]
101 movdqu xmm3, XMMWORD PTR [rsi+rax+16]
104 movdqu xmm2, XMMWORD PTR [rdi+rdx+16]
[all …]
Dsad_ssse3.asm16 movdqa xmm0, XMMWORD PTR [rsi]
17 lddqu xmm5, XMMWORD PTR [rdi]
18 lddqu xmm6, XMMWORD PTR [rdi+1]
19 lddqu xmm7, XMMWORD PTR [rdi+2]
25 movdqa xmm0, XMMWORD PTR [rsi]
26 lddqu xmm1, XMMWORD PTR [rdi]
27 lddqu xmm2, XMMWORD PTR [rdi+1]
28 lddqu xmm3, XMMWORD PTR [rdi+2]
38 movdqa xmm0, XMMWORD PTR [rsi+rax]
39 lddqu xmm1, XMMWORD PTR [rdi+rdx]
[all …]
/external/libvpx/libvpx/vp8/encoder/x86/
Ddct_sse2.asm69 movq xmm0, MMWORD PTR[input ] ;03 02 01 00
70 movq xmm2, MMWORD PTR[input+ pitch] ;13 12 11 10
72 movq xmm1, MMWORD PTR[input ] ;23 22 21 20
73 movq xmm3, MMWORD PTR[input+ pitch] ;33 32 31 30
94 pmaddwd xmm0, XMMWORD PTR[GLOBAL(_mult_add)] ;a1 + b1
95 pmaddwd xmm1, XMMWORD PTR[GLOBAL(_mult_sub)] ;a1 - b1
97 pmaddwd xmm3, XMMWORD PTR[GLOBAL(_5352_2217)] ;c1*2217 + d1*5352
98 pmaddwd xmm4, XMMWORD PTR[GLOBAL(_2217_neg5352)];d1*2217 - c1*5352
100 paddd xmm3, XMMWORD PTR[GLOBAL(_14500)]
101 paddd xmm4, XMMWORD PTR[GLOBAL(_7500)]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dnacl-mem-intrinsics.ll73 ; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
74 ; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
92 ; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
93 ; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
94 ; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x2]
95 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],[[REG]]
113 ; CHECK: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}]
114 ; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG]]
115 ; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x8]
116 ; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],[[REG]]
[all …]
Drandomize-regalloc.ll26 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
27 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
28 ; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
29 ; OPTM1_1-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x20],0x31
30 ; OPTM1_1-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x10],0x31
31 ; OPTM1_1-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
35 ; OPTM1_1-NEXT: movups XMMWORD PTR [esp],xmm0
36 ; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp]
53 ; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
54 ; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
[all …]
Dnacl-atomic-fence-all.ll43 ; CHECK: mov DWORD PTR {{.*}},0x3e7
46 ; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_a)|(.bss)}}
47 ; CHECK: mov {{(DWORD PTR)?}}
49 ; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_b)|(.bss)}}
50 ; CHECK: mov {{(DWORD PTR)?}}
51 ; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_c)|(.bss)}}
53 ; CHECK: mov {{(DWORD PTR)?}}
82 ; CHECK: mov DWORD PTR {{.*}},0x3e7
84 ; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_a)|(.bss)}}
85 ; CHECK: mov {{(DWORD PTR)?}}
[all …]
Debp_args.ll33 ; CHECK: mov DWORD PTR [ebp-0x4],eax
34 ; CHECK: mov eax,DWORD PTR [ebp+0xc]
35 ; CHECK: mov BYTE PTR [ebp-0x8],al
36 ; CHECK: movzx eax,BYTE PTR [ebp-0x8]
37 ; CHECK: mov DWORD PTR [ebp-0xc],eax
38 ; CHECK: mov eax,DWORD PTR [ebp+0x8]
39 ; CHECK: mov DWORD PTR [esp],eax
40 ; CHECK: mov eax,DWORD PTR [ebp-0x4]
41 ; CHECK: mov DWORD PTR [esp+0x4],eax
42 ; CHECK: mov eax,DWORD PTR [ebp-0xc]
[all …]
Drmw.ll16 ; Look for something like: add DWORD PTR [eax],ecx
18 ; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],e{{ax|bx|cx|dx|bp|di|si}}
28 ; Look for something like: add DWORD PTR [eax],0x13
30 ; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x13
41 ; CHECK: add e{{ax|bx|cx|dx|bp|di|si}},DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}]
52 ; Look for something like: add WORD PTR [eax],cx
54 ; CHECK: add WORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],{{ax|bx|cx|dx|bp|di|si}}
64 ; Look for something like: add WORD PTR [eax],0x13
66 ; CHECK: add WORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x13
77 ; Look for something like: add BYTE PTR [eax],cl
[all …]
Dvector-arg.ll28 ; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
29 ; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
52 ; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
53 ; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
78 ; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
79 ; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
104 ; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
105 ; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
126 ; CHECK: movups xmm0,XMMWORD PTR [esp+0x4]
130 ; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
[all …]
/external/swiftshader/third_party/subzero/tests_lit/asan_tests/
Dalignment.ll19 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000000],0xffffffff
20 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000004],0xffffff04
21 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000008],0xffffffff
22 ; CHECK-NEXT: mov DWORD PTR [eax+0x2000000c],0xffffff05
23 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000010],0xffffffff
24 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000000],0x0
25 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000004],0x0
26 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000008],0x0
27 ; CHECK-NEXT: mov DWORD PTR [eax+0x2000000c],0x0
28 ; CHECK-NEXT: mov DWORD PTR [eax+0x20000010],0x0
/external/llvm/test/MC/X86/
Dintel-syntax.s11 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP + 4], 258
15 mov QWORD PTR [RSP - 16], 123
17 mov BYTE PTR [RSP - 17], 97
19 mov EAX, DWORD PTR [RSP - 4]
21 mov RAX, QWORD PTR [RSP]
23 mov DWORD PTR [RSP - 4], -4
25 mov RCX, QWORD PTR [0]
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
29 mov BYTE PTR [RDX + RCX], DIL
[all …]
Dintel-syntax-x86-64-avx512f_vl.s17 vcmppd k3,xmm27,XMMWORD PTR [rcx],0x7b
21 vcmppd k3,xmm27,XMMWORD PTR [rax+r14*8+0x123],0x7b
25 vcmppd k3,xmm27,QWORD PTR [rcx]{1to2},0x7b
29 vcmppd k3,xmm27,XMMWORD PTR [rdx+0x7f0],0x7b
33 vcmppd k3,xmm27,XMMWORD PTR [rdx+0x800],0x7b
37 vcmppd k3,xmm27,XMMWORD PTR [rdx-0x800],0x7b
41 vcmppd k3,xmm27,XMMWORD PTR [rdx-0x810],0x7b
45 vcmppd k3,xmm27,QWORD PTR [rdx+0x3f8]{1to2},0x7b
49 vcmppd k3,xmm27,QWORD PTR [rdx+0x400]{1to2},0x7b
53 vcmppd k3,xmm27,QWORD PTR [rdx-0x400]{1to2},0x7b
[all …]
/external/syslinux/lzo/src/
Dlzo_ptr.h59 #define PTR(a) ((lzo_uintptr_t) (a))
60 #define PTR_LINEAR(a) PTR(a)
67 #define PTR_LT(a,b) (PTR(a) < PTR(b))
68 #define PTR_GE(a,b) (PTR(a) >= PTR(b))
69 #define PTR_DIFF(a,b) (PTR(a) - PTR(b))
/external/swiftshader/third_party/subzero/tests_lit/assembler/x86/
Dsandboxing.ll42 ; CHECK: mov [[REG:.*]],DWORD PTR [esp
86 ; CHECK-NEXT: 20: {{.*}} mov BYTE PTR
87 ; CHECK-NEXT: 27: {{.*}} mov WORD PTR
88 ; CHECK-NEXT: 30: {{.*}} mov BYTE PTR
89 ; CHECK-NEXT: 37: {{.*}} mov WORD PTR
90 ; CHECK-NEXT: 40: {{.*}} mov BYTE PTR
91 ; CHECK-NEXT: 47: {{.*}} mov WORD PTR
109 ; CHECK-NEXT: 20: {{.*}} mov WORD PTR
110 ; CHECK-NEXT: 29: {{.*}} mov WORD PTR
111 ; CHECK-NEXT: 32: {{.*}} mov WORD PTR
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Dreturn-struct.ll129 ; N64-LE-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1)
130 ; N64-LE-DAG: lh [[R1:\$[0-9]+]], 4([[PTR]])
131 ; N64-LE-DAG: lwu [[R2:\$[0-9]+]], 0([[PTR]])
135 ; N64-BE-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_3xi16)($1)
136 ; N64-BE-DAG: lw [[R1:\$[0-9]+]], 0([[PTR]])
138 ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]])
154 ; O32-DAG: lui [[PTR:\$[0-9]+]], %hi(struct_128xi16)
155 ; O32-DAG: addiu $5, [[PTR]], %lo(struct_128xi16)
160 ; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
182 ; O32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32)
[all …]

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