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Searched refs:PUSH_DATA (Results 1 – 25 of 81) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/nouveau/
Dnv20_context.c68 PUSH_DATA (push, pack_rgba_clamp_f(s->format, ctx->Color.ClearColor.f)); in nv20_clear()
83 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear, in nv20_clear()
90 PUSH_DATA (push, clear); in nv20_clear()
105 PUSH_DATA (push, hw->eng3d->handle); in nv20_hwctx_init()
107 PUSH_DATA (push, hw->ntfy->handle); in nv20_hwctx_init()
109 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
110 PUSH_DATA (push, fifo->gart); in nv20_hwctx_init()
112 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
113 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
115 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
[all …]
Dnv10_context.c155 PUSH_DATA (push, pack_zs_f(s->format, ctx->Depth.Clear, 0)); in nv17_zclear()
157 PUSH_DATA (push, 1); in nv17_zclear()
209 PUSH_DATA (push, hw->eng3d->handle); in nv10_hwctx_init()
211 PUSH_DATA (push, hw->ntfy->handle); in nv10_hwctx_init()
214 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
215 PUSH_DATA (push, fifo->gart); in nv10_hwctx_init()
216 PUSH_DATA (push, fifo->gart); in nv10_hwctx_init()
218 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
219 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
222 PUSH_DATA (push, 0); in nv10_hwctx_init()
[all …]
Dnv04_surface.c220 PUSH_DATA (push, swzsurf->handle); in nv04_surface_copy_swizzle()
234 PUSH_DATA (push, fifo->vram); in nv04_surface_copy_swizzle()
236 PUSH_DATA (push, swzsurf_format(dst->format) | in nv04_surface_copy_swizzle()
244 PUSH_DATA (push, swzsurf->handle); in nv04_surface_copy_swizzle()
247 PUSH_DATA (push, sifm_format(src->format)); in nv04_surface_copy_swizzle()
248 PUSH_DATA (push, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY); in nv04_surface_copy_swizzle()
249 PUSH_DATA (push, (y + dy) << 16 | (x + dx)); in nv04_surface_copy_swizzle()
250 PUSH_DATA (push, sub_h << 16 | sub_w); in nv04_surface_copy_swizzle()
251 PUSH_DATA (push, (y + dy) << 16 | (x + dx)); in nv04_surface_copy_swizzle()
252 PUSH_DATA (push, sub_h << 16 | sub_w); in nv04_surface_copy_swizzle()
[all …]
Dnv10_state_raster.c46 PUSH_DATA (push, nvgl_comparison_op(ctx->Color.AlphaFunc)); in nv10_emit_alpha_func()
47 PUSH_DATA (push, FLOAT_TO_UBYTE(ctx->Color.AlphaRef)); in nv10_emit_alpha_func()
56 PUSH_DATA (push, FLOAT_TO_UBYTE(ctx->Color.BlendColor[3]) << 24 | in nv10_emit_blend_color()
71 PUSH_DATA (push, nvgl_blend_eqn(ctx->Color.Blend[0].EquationRGB)); in nv10_emit_blend_equation()
80 PUSH_DATA (push, nvgl_blend_func(ctx->Color.Blend[0].SrcRGB)); in nv10_emit_blend_func()
81 PUSH_DATA (push, nvgl_blend_func(ctx->Color.Blend[0].DstRGB)); in nv10_emit_blend_func()
90 PUSH_DATA (push, ((ctx->Color.ColorMask[0][3] ? 1 << 24 : 0) | in nv10_emit_color_mask()
107 PUSH_DATA (push, nvgl_comparison_op(ctx->Depth.Func)); in nv10_emit_depth()
129 PUSH_DATA (push, nvgl_logicop_func(ctx->Color.LogicOp)); in nv10_emit_logic_opcode()
138 PUSH_DATA (push, ctx->Light.ShadeModel == GL_SMOOTH ? in nv10_emit_shade_model()
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_compute.c59 PUSH_DATA (push, screen->compute->oclass); in nvc0_screen_compute_setup()
63 PUSH_DATA (push, screen->mp_count); in nvc0_screen_compute_setup()
65 PUSH_DATA (push, 0xf); in nvc0_screen_compute_setup()
68 PUSH_DATA (push, 0x8000); in nvc0_screen_compute_setup()
72 PUSH_DATA (push, 0); in nvc0_screen_compute_setup()
75 PUSH_DATA (push, (0xc << 28) | (i << 16) | i); in nvc0_screen_compute_setup()
77 PUSH_DATA (push, 1); in nvc0_screen_compute_setup()
82 PUSH_DATA (push, screen->tls->offset); in nvc0_screen_compute_setup()
85 PUSH_DATA (push, screen->tls->size); in nvc0_screen_compute_setup()
87 PUSH_DATA (push, 0); in nvc0_screen_compute_setup()
[all …]
Dnve4_compute.c73 PUSH_DATA (push, screen->compute->oclass); in nve4_screen_compute_setup()
77 PUSH_DATA (push, screen->tls->offset); in nve4_screen_compute_setup()
84 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff); in nve4_screen_compute_setup()
85 PUSH_DATA (push, 0xff); in nve4_screen_compute_setup()
88 PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff); in nve4_screen_compute_setup()
89 PUSH_DATA (push, 0xff); in nve4_screen_compute_setup()
97 PUSH_DATA (push, 0xff << 24); in nve4_screen_compute_setup()
99 PUSH_DATA (push, 0xfe << 24); in nve4_screen_compute_setup()
103 PUSH_DATA (push, screen->text->offset); in nve4_screen_compute_setup()
106 PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300); in nve4_screen_compute_setup()
[all …]
Dnvc0_screen.c568 PUSH_DATA (push, (m - 0x3800) / 8); in nvc0_graph_set_macro()
569 PUSH_DATA (push, pos); in nvc0_graph_set_macro()
571 PUSH_DATA (push, pos); in nvc0_graph_set_macro()
581 PUSH_DATA (push, 0xff); in nvc0_magic_3d_init()
583 PUSH_DATA (push, 0xff); in nvc0_magic_3d_init()
584 PUSH_DATA (push, 0xff); in nvc0_magic_3d_init()
586 PUSH_DATA (push, 0xff); in nvc0_magic_3d_init()
587 PUSH_DATA (push, 0xff); in nvc0_magic_3d_init()
589 PUSH_DATA (push, 0x3f); in nvc0_magic_3d_init()
592 PUSH_DATA (push, (3 << 16) | 3); in nvc0_magic_3d_init()
[all …]
Dnvc0_state_validate.c33 PUSH_DATA (push, 0);
36 PUSH_DATA (push, bo->offset + offset);
40 PUSH_DATA (push, bo->offset + offset);
42 PUSH_DATA (push, size);
43 PUSH_DATA (push, size >> 16);
45 PUSH_DATA (push, 2);
47 PUSH_DATA (push, width);
48 PUSH_DATA (push, height);
49 PUSH_DATA (push, 1);
50 PUSH_DATA (push, 0);
[all …]
Dnvc0_shader_state.c78 PUSH_DATA (push, 0x11); in nvc0_vertprog_validate()
79 PUSH_DATA (push, vp->code_base); in nvc0_vertprog_validate()
81 PUSH_DATA (push, vp->num_gprs); in nvc0_vertprog_validate()
133 PUSH_DATA (push, hwflatshade ? NVC0_3D_SHADE_MODEL_FLAT : in nvc0_fragprog_validate()
151 PUSH_DATA (push, 0x51); in nvc0_fragprog_validate()
152 PUSH_DATA (push, fp->code_base); in nvc0_fragprog_validate()
154 PUSH_DATA (push, fp->num_gprs); in nvc0_fragprog_validate()
157 PUSH_DATA (push, 0x20164010); in nvc0_fragprog_validate()
158 PUSH_DATA (push, 0x20); in nvc0_fragprog_validate()
160 PUSH_DATA (push, fp->flags[0]); in nvc0_fragprog_validate()
[all …]
Dnvc0_transfer.c39 PUSH_DATA (push, src->tile_mode); in nvc0_m2mf_transfer_rect()
40 PUSH_DATA (push, src->width * cpp); in nvc0_m2mf_transfer_rect()
41 PUSH_DATA (push, src->height); in nvc0_m2mf_transfer_rect()
42 PUSH_DATA (push, src->depth); in nvc0_m2mf_transfer_rect()
43 PUSH_DATA (push, src->z); in nvc0_m2mf_transfer_rect()
48 PUSH_DATA (push, src->width * cpp); in nvc0_m2mf_transfer_rect()
55 PUSH_DATA (push, dst->tile_mode); in nvc0_m2mf_transfer_rect()
56 PUSH_DATA (push, dst->width * cpp); in nvc0_m2mf_transfer_rect()
57 PUSH_DATA (push, dst->height); in nvc0_m2mf_transfer_rect()
58 PUSH_DATA (push, dst->depth); in nvc0_m2mf_transfer_rect()
[all …]
Dnvc0_video_bsp.c177 PUSH_DATA (push, caps); // 700 cmd in nvc0_decoder_bsp_end()
178 PUSH_DATA (push, bsp_addr + 1); // 704 strparm_bsp in nvc0_decoder_bsp_end()
179 PUSH_DATA (push, bsp_addr + 7); // 708 str addr in nvc0_decoder_bsp_end()
180 PUSH_DATA (push, comm_addr); // 70c comm in nvc0_decoder_bsp_end()
181 PUSH_DATA (push, comm_seq); // 710 seq in nvc0_decoder_bsp_end()
190 PUSH_DATA (push, bsp_addr); // 400 picparm addr in nvc0_decoder_bsp_end()
191 PUSH_DATA (push, inter_addr); // 404 interparm addr in nvc0_decoder_bsp_end()
192 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr in nvc0_decoder_bsp_end()
193 PUSH_DATA (push, ring_size << 8); // 40c interdata_size in nvc0_decoder_bsp_end()
194 PUSH_DATA (push, bitplane_addr); // 410 BITPLANE_DATA in nvc0_decoder_bsp_end()
[all …]
Dnvc0_surface.c119 PUSH_DATA (push, format); in nvc0_2d_texture_set()
120 PUSH_DATA (push, 1); in nvc0_2d_texture_set()
122 PUSH_DATA (push, mt->level[level].pitch); in nvc0_2d_texture_set()
123 PUSH_DATA (push, width); in nvc0_2d_texture_set()
124 PUSH_DATA (push, height); in nvc0_2d_texture_set()
126 PUSH_DATA (push, bo->offset + offset); in nvc0_2d_texture_set()
129 PUSH_DATA (push, format); in nvc0_2d_texture_set()
130 PUSH_DATA (push, 0); in nvc0_2d_texture_set()
131 PUSH_DATA (push, mt->level[level].tile_mode); in nvc0_2d_texture_set()
132 PUSH_DATA (push, depth); in nvc0_2d_texture_set()
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nv50/
Dnv50_compute.c71 PUSH_DATA (push, screen->compute->handle); in nv50_screen_compute_setup()
74 PUSH_DATA (push, 1); in nv50_screen_compute_setup()
76 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
79 PUSH_DATA (push, screen->stack_bo->offset); in nv50_screen_compute_setup()
81 PUSH_DATA (push, 4); in nv50_screen_compute_setup()
84 PUSH_DATA (push, 1); in nv50_screen_compute_setup()
86 PUSH_DATA (push, 1); in nv50_screen_compute_setup()
88 PUSH_DATA (push, NV50_COMPUTE_REG_MODE_STRIPED); in nv50_screen_compute_setup()
90 PUSH_DATA (push, 0x100); in nv50_screen_compute_setup()
92 PUSH_DATA (push, fifo->vram); in nv50_screen_compute_setup()
[all …]
Dnv50_screen.c501 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4)); in nv50_screen_fence_emit()
503 PUSH_DATA (push, screen->fence.bo->offset); in nv50_screen_fence_emit()
504 PUSH_DATA (push, *sequence); in nv50_screen_fence_emit()
505 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | in nv50_screen_fence_emit()
529 PUSH_DATA (push, screen->m2mf->handle); in nv50_screen_init_hwctx()
531 PUSH_DATA (push, screen->sync->handle); in nv50_screen_init_hwctx()
532 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
533 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
536 PUSH_DATA (push, screen->eng2d->handle); in nv50_screen_init_hwctx()
538 PUSH_DATA (push, screen->sync->handle); in nv50_screen_init_hwctx()
[all …]
Dnv50_surface.c116 PUSH_DATA (push, format); in nv50_2d_texture_set()
117 PUSH_DATA (push, 1); in nv50_2d_texture_set()
119 PUSH_DATA (push, mt->level[level].pitch); in nv50_2d_texture_set()
120 PUSH_DATA (push, width); in nv50_2d_texture_set()
121 PUSH_DATA (push, height); in nv50_2d_texture_set()
123 PUSH_DATA (push, mt->base.address + offset); in nv50_2d_texture_set()
126 PUSH_DATA (push, format); in nv50_2d_texture_set()
127 PUSH_DATA (push, 0); in nv50_2d_texture_set()
128 PUSH_DATA (push, mt->level[level].tile_mode); in nv50_2d_texture_set()
129 PUSH_DATA (push, depth); in nv50_2d_texture_set()
[all …]
Dnv50_transfer.c78 PUSH_DATA (push, 0); in nv50_m2mf_transfer_rect()
79 PUSH_DATA (push, src->tile_mode); in nv50_m2mf_transfer_rect()
80 PUSH_DATA (push, src->width * cpp); in nv50_m2mf_transfer_rect()
81 PUSH_DATA (push, src->height); in nv50_m2mf_transfer_rect()
82 PUSH_DATA (push, src->depth); in nv50_m2mf_transfer_rect()
83 PUSH_DATA (push, src->z); in nv50_m2mf_transfer_rect()
88 PUSH_DATA (push, 1); in nv50_m2mf_transfer_rect()
90 PUSH_DATA (push, src->pitch); in nv50_m2mf_transfer_rect()
95 PUSH_DATA (push, 0); in nv50_m2mf_transfer_rect()
96 PUSH_DATA (push, dst->tile_mode); in nv50_m2mf_transfer_rect()
[all …]
Dnv98_video_bsp.c124 PUSH_DATA (push, caps); // 700 cmd in nv98_decoder_bsp()
125 PUSH_DATA (push, bsp_addr + 1); // 704 strparm_bsp in nv98_decoder_bsp()
126 PUSH_DATA (push, bsp_addr + 7); // 708 str addr in nv98_decoder_bsp()
127 PUSH_DATA (push, comm_addr); // 70c comm in nv98_decoder_bsp()
128 PUSH_DATA (push, comm_seq); // 710 seq in nv98_decoder_bsp()
138 PUSH_DATA (push, bsp_addr); // 400 picparm addr in nv98_decoder_bsp()
139 PUSH_DATA (push, inter_addr); // 404 interparm addr in nv98_decoder_bsp()
140 PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr in nv98_decoder_bsp()
141 PUSH_DATA (push, ring_size << 8); // 40c interdata_size in nv98_decoder_bsp()
143 PUSH_DATA (push, bitplane_addr); // 410 BITPLANE_DATA in nv98_decoder_bsp()
[all …]
Dnv50_state_validate.c10 PUSH_DATA (push, 0); in nv50_fb_set_null_rt()
11 PUSH_DATA (push, 0); in nv50_fb_set_null_rt()
12 PUSH_DATA (push, 0); in nv50_fb_set_null_rt()
13 PUSH_DATA (push, 0); in nv50_fb_set_null_rt()
15 PUSH_DATA (push, 64); in nv50_fb_set_null_rt()
16 PUSH_DATA (push, 0); in nv50_fb_set_null_rt()
31 PUSH_DATA (push, (076543210 << 4) | fb->nr_cbufs); in nv50_validate_fb()
33 PUSH_DATA (push, fb->width << 16); in nv50_validate_fb()
34 PUSH_DATA (push, fb->height << 16); in nv50_validate_fb()
59 PUSH_DATA (push, mt->base.address + sf->offset); in nv50_validate_fb()
[all …]
Dnv84_video_bsp.c208 PUSH_DATA (push, dec->fence->offset); in nv84_decoder_bsp()
209 PUSH_DATA (push, 1); in nv84_decoder_bsp()
210 PUSH_DATA (push, 1); in nv84_decoder_bsp()
216 PUSH_DATA (push, dec->bitstream->offset >> 8); in nv84_decoder_bsp()
217 PUSH_DATA (push, (dec->bitstream->offset >> 8) + 7); in nv84_decoder_bsp()
218 PUSH_DATA (push, dec->bitstream->size / 2 - 0x700); in nv84_decoder_bsp()
219 PUSH_DATA (push, (dec->bitstream->offset >> 8) + 6); in nv84_decoder_bsp()
220 PUSH_DATA (push, 1); in nv84_decoder_bsp()
221 PUSH_DATA (push, dec->mbring->offset >> 8); in nv84_decoder_bsp()
222 PUSH_DATA (push, dec->frame_size); in nv84_decoder_bsp()
[all …]
Dnv84_video_vp.c155 PUSH_DATA (push, dec->fence->offset); in nv84_decoder_vp_h264()
156 PUSH_DATA (push, 2); in nv84_decoder_vp_h264()
157 PUSH_DATA (push, 1); /* wait for sem == 2 */ in nv84_decoder_vp_h264()
161 PUSH_DATA (push, 1); in nv84_decoder_vp_h264()
162 PUSH_DATA (push, param2.mbs); in nv84_decoder_vp_h264()
163 PUSH_DATA (push, 0x3987654); /* each nibble probably a dma index */ in nv84_decoder_vp_h264()
164 PUSH_DATA (push, 0x55001); /* constant */ in nv84_decoder_vp_h264()
165 PUSH_DATA (push, dec->vp_params->offset >> 8); in nv84_decoder_vp_h264()
166 PUSH_DATA (push, (dec->vpring->offset + dec->vpring_residual) >> 8); in nv84_decoder_vp_h264()
167 PUSH_DATA (push, dec->vpring_ctrl); in nv84_decoder_vp_h264()
[all …]
Dnv50_shader_state.c68 PUSH_DATA (push, (b << 12) | (i << 8) | p | 1); in nv50_constbufs_validate()
75 PUSH_DATA (push, (start << 8) | b); in nv50_constbufs_validate()
93 PUSH_DATA (push, res->address + nv50->constbuf[s][i].offset); in nv50_constbufs_validate()
94 PUSH_DATA (push, (b << 16) | in nv50_constbufs_validate()
97 PUSH_DATA (push, (b << 12) | (i << 8) | p | 1); in nv50_constbufs_validate()
105 PUSH_DATA (push, (i << 8) | p | 0); in nv50_constbufs_validate()
160 PUSH_DATA (push, vp->vp.attrs[0]); in nv50_vertprog_validate()
161 PUSH_DATA (push, vp->vp.attrs[1]); in nv50_vertprog_validate()
163 PUSH_DATA (push, vp->max_out); in nv50_vertprog_validate()
165 PUSH_DATA (push, vp->max_gpr); in nv50_vertprog_validate()
[all …]
Dnv50_tex.c254 PUSH_DATA (push, (i << 1) | 0); in nv50_validate_tic()
264 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM); in nv50_validate_tic()
265 PUSH_DATA (push, 1); in nv50_validate_tic()
267 PUSH_DATA (push, 262144); in nv50_validate_tic()
268 PUSH_DATA (push, 65536); in nv50_validate_tic()
269 PUSH_DATA (push, 1); in nv50_validate_tic()
271 PUSH_DATA (push, txc->offset); in nv50_validate_tic()
273 PUSH_DATA (push, 0); in nv50_validate_tic()
274 PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM); in nv50_validate_tic()
276 PUSH_DATA (push, 32); in nv50_validate_tic()
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_transfer.c93 PUSH_DATA (push, vp->start); in nv30_transfer_rect_vertprog()
95 PUSH_DATA (push, 0x401f9c6c); /* mov o[hpos], a[0]; */ in nv30_transfer_rect_vertprog()
96 PUSH_DATA (push, 0x0040000d); in nv30_transfer_rect_vertprog()
97 PUSH_DATA (push, 0x8106c083); in nv30_transfer_rect_vertprog()
98 PUSH_DATA (push, 0x6041ff80); in nv30_transfer_rect_vertprog()
100 PUSH_DATA (push, 0x401f9c6c); /* mov o[tex0], a[8]; end; */ in nv30_transfer_rect_vertprog()
101 PUSH_DATA (push, 0x0040080d); in nv30_transfer_rect_vertprog()
102 PUSH_DATA (push, 0x8106c083); in nv30_transfer_rect_vertprog()
103 PUSH_DATA (push, 0x6041ff9d); in nv30_transfer_rect_vertprog()
199 PUSH_DATA (push, dst->w << 16); in nv30_transfer_rect_blit()
[all …]
Dnv30_clear.c79 PUSH_DATA (push, 0); in nv30_clear()
80 PUSH_DATA (push, 0x000000ff); in nv30_clear()
88 PUSH_DATA (push, zeta); in nv30_clear()
89 PUSH_DATA (push, colr); in nv30_clear()
90 PUSH_DATA (push, mode); in nv30_clear()
94 PUSH_DATA (push, zeta); in nv30_clear()
95 PUSH_DATA (push, colr); in nv30_clear()
96 PUSH_DATA (push, mode); in nv30_clear()
136 PUSH_DATA (push, NV30_3D_RT_ENABLE_COLOR0); in nv30_clear_render_target()
138 PUSH_DATA (push, sf->width << 16); in nv30_clear_render_target()
[all …]
Dnv30_screen.c400 PUSH_DATA (push, NV30_3D_FENCE_OFFSET | in nv30_screen_fence_emit()
402 PUSH_DATA (push, 0); in nv30_screen_fence_emit()
403 PUSH_DATA (push, *sequence); in nv30_screen_fence_emit()
618 PUSH_DATA (push, screen->eng3d->handle); in nv30_screen_create()
620 PUSH_DATA (push, screen->ntfy->handle); in nv30_screen_create()
621 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */ in nv30_screen_create()
622 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */ in nv30_screen_create()
623 PUSH_DATA (push, fifo->vram); /* COLOR1 */ in nv30_screen_create()
624 PUSH_DATA (push, screen->null->handle); /* UNK190 */ in nv30_screen_create()
625 PUSH_DATA (push, fifo->vram); /* COLOR0 */ in nv30_screen_create()
[all …]

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