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Searched refs:PrintReg (Results 1 – 25 of 70) sorted by relevance

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/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
117 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
DRegAllocFast.cpp289 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) in spillVirtReg()
290 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
459 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); in calcSpillCost()
468 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " in calcSpillCost()
469 << PrintReg(PhysReg, TRI) << " is reserved already.\n"); in calcSpillCost()
479 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); in calcSpillCost()
508 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " in assignVirtToPhysReg()
509 << PrintReg(PhysReg, TRI) << "\n"); in assignVirtToPhysReg()
563 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " in allocVirtReg()
569 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); in allocVirtReg()
[all …]
DRegAllocGreedy.cpp635 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); in tryAssign()
651 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost in tryAssign()
682 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) in canReassign()
816 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) in evictInterference()
900 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " in tryEvict()
901 << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1422 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCost()
1425 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost()
1433 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCost()
1482 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " in doRegionSplit()
[all …]
DRegisterCoalescer.cpp539 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI)); in adjustCopiesBackFrom()
1416 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) in joinCopy()
1417 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) in joinCopy()
1439 dbgs() << PrintReg(CP.getDstReg()) << " in " in joinCopy()
1441 << PrintReg(CP.getSrcReg()) << " in " in joinCopy()
1444 dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in " in joinCopy()
1445 << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; in joinCopy()
1531 dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) in joinCopy()
1532 << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; in joinCopy()
1535 dbgs() << PrintReg(CP.getDstReg(), TRI); in joinCopy()
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DMachineRegisterInfo.cpp159 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
168 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
174 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
180 errs() << PrintReg(Reg, getTargetRegisterInfo()) in verifyUseList()
DRenameIndependentSubregs.cpp137 DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses() in INITIALIZE_PASS_DEPENDENCY()
139 DEBUG(dbgs() << PrintReg(Reg) << ": Splitting into newly created:"); in INITIALIZE_PASS_DEPENDENCY()
145 DEBUG(dbgs() << ' ' << PrintReg(NewVReg)); in INITIALIZE_PASS_DEPENDENCY()
DAllocationOrder.cpp45 dbgs() << ' ' << PrintReg(Hints[I], TRI); in AllocationOrder()
DVirtRegMap.cpp123 OS << '[' << PrintReg(Reg, TRI) << " -> " in print()
124 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " in print()
132 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] in print()
DTargetRegisterInfo.cpp45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() function
397 dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
DRegAllocPBQP.cpp647 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: " in spillVReg()
656 DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " "); in spillVReg()
686 DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> " in mapPBQPToRegAlloc()
836 OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')'; in PrintNodeInfo()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocFast.cpp264 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI) in spillVirtReg()
265 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
426 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); in calcSpillCost()
435 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " in calcSpillCost()
436 << PrintReg(PhysReg, TRI) << " is reserved already.\n"); in calcSpillCost()
443 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); in calcSpillCost()
471 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to " in assignVirtToPhysReg()
472 << PrintReg(PhysReg, TRI) << "\n"); in assignVirtToPhysReg()
512 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " in allocVirtReg()
518 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); in allocVirtReg()
[all …]
DRegAllocBasic.cpp277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
278 << " to " << PrintReg(PhysReg, TRI) << '\n'); in assign()
287 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
288 << " from " << PrintReg(PhysReg, TRI) << '\n'); in unassign()
441 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:"); in addMBBLiveIns()
453 << PrintReg(SI.value()->reg, TRI)); in addMBBLiveIns()
DRegAllocGreedy.cpp461 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); in tryAssign()
476 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost in tryAssign()
591 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) in evictInterference()
639 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " in tryEvict()
640 << PrintReg(CSR, TRI) << '\n'); in tryEvict()
1131 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); in tryRegionSplit()
1134 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost); in tryRegionSplit()
1141 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in tryRegionSplit()
1187 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " in tryRegionSplit()
1393 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' in tryLocalSplit()
[all …]
DLiveIntervalUnion.cpp82 OS << "LIU " << PrintReg(RepReg, TRI); in print()
89 << PrintReg(SI.value()->reg, TRI); in print()
DInlineSpiller.cpp317 OS << "spill " << PrintReg(SVI.SpillReg) << ':' in operator <<()
482 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':' in traceSiblingValue()
487 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':' in traceSiblingValue()
499 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def in traceSiblingValue()
586 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':' in traceSiblingValue()
657 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@' in analyzeSiblingValues()
682 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n'); in hoistSpill()
689 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n'); in hoistSpill()
1092 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); in spillAroundUses()
DVirtRegMap.cpp363 OS << '[' << PrintReg(Reg, TRI) << " -> " in print()
364 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " in print()
372 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] in print()
DRegisterClassInfo.cpp110 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
DMachineFunction.cpp307 OS << PrintReg(I->first, TRI); in print()
309 OS << " in " << PrintReg(I->second, TRI); in print()
319 OS << ' ' << PrintReg(*I, TRI); in print()
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp250 DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to " in addInterChainConstraint()
251 << PrintReg(Rd, TRI) << '\n';); in addInterChainConstraint()
256 DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI) in addInterChainConstraint()
343 DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "; in apply()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h700 class PrintReg {
705 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
710 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp171 OS << ' ' << PrintReg(R, P.TRI); in operator <<()
402 OS << PrintReg(*I, P.TRI); in operator <<()
448 OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI) in operator <<()
542 dbgs() << " " << PrintReg(I->first, HRI) << ":\n"; in dump_map()
760 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI) in findRecordInsertForms()
824 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n"; in findRecordInsertForms()
829 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
877 dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI) in findRecordInsertForms()
878 << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
1516 dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
DHexagonGenPredicate.cpp58 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
206 << PrintReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
210 DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
DBitTracker.cpp815 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) in visitPHI()
822 dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) in visitPHI()
847 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) in visitNonBranch()
854 dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: " in visitNonBranch()
977 dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; in visitUsesOf()
1124 dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n"; in run()
DHexagonSplitDouble.cpp115 dbgs() << ' ' << PrintReg(I, &TRI); in dump_partition()
226 DEBUG(dbgs() << PrintReg(R, TRI) << " ~~"); in partitionRegisters()
249 DEBUG(dbgs() << ' ' << PrintReg(T, TRI)); in partitionRegisters()
1112 DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> " in splitPartition()
1113 << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n'); in splitPartition()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp32 void PrintReg::print(raw_ostream &OS) const { in print()

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