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Searched refs:QPU_UPDATE_FIELD (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.c38 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_A); in set_src_raddr()
45 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_B); in set_src_raddr()
243 inst = QPU_UPDATE_FIELD(inst, QPU_SIG_SMALL_IMM, QPU_SIG); in qpu_m_rot()
244 inst = QPU_UPDATE_FIELD(inst, QPU_SMALL_IMM_MUL_ROT + rot, in qpu_m_rot()
394 *merge = QPU_UPDATE_FIELD(*merge, raddr_b_a, QPU_RADDR_A); in try_swap_ra_file()
395 *merge = QPU_UPDATE_FIELD(*merge, raddr_a_a, QPU_RADDR_B); in try_swap_ra_file()
424 *inst = QPU_UPDATE_FIELD(*inst, QPU_A_NOP, QPU_OP_ADD); in convert_mov()
425 *inst = QPU_UPDATE_FIELD(*inst, QPU_M_V8MIN, QPU_OP_MUL); in convert_mov()
427 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_A); in convert_mov()
428 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_B); in convert_mov()
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Dvc4_qpu_defines.h240 #define QPU_UPDATE_FIELD(inst, value, field) \ macro
Dvc4_qpu_schedule.c876 QPU_UPDATE_FIELD(c->qpu_insts[thrsw_ip], sig, QPU_SIG); in emit_thrsw()
/external/libdrm/vc4/
Dvc4_qpu_defines.h220 #define QPU_UPDATE_FIELD(inst, value, field) \ macro