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Searched refs:R10 (Results 1 – 25 of 128) sorted by relevance

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/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s22 MOVQ DX,R10
27 ADDQ ·_2P1234(SB),R10
37 SUBQ 88(DI),R10
47 MOVQ R10,48(SP)
63 MOVQ AX,R10
77 ADDQ AX,R10
116 ADDQ AX,R10
129 SHLQ $13,R11:R10
130 ANDQ DX,R10
131 ADDQ R9,R10
[all …]
Dmul_amd64.s37 MOVQ AX,R10
53 ADDQ AX,R10
92 ADDQ AX,R10
104 ADDQ AX,R10
116 ADDQ AX,R10
129 SHLQ $13,R11:R10
130 ANDQ SI,R10
131 ADDQ R9,R10
145 ADDQ R10,DX
158 MOVQ DX,R10
[all …]
Dsquare_amd64.s25 MOVQ DX,R10
73 ADCQ DX,R10
78 ADCQ DX,R10
92 SHLQ $13,R10:R9
97 ADDQ R10,R11
122 MOVQ DX,R10
126 ANDQ SI,R10
131 MOVQ R10,32(DI)
Dfreeze_amd64.s22 MOVQ AX,R10
23 SUBQ $18,R10
50 CMPQ R10,SI
62 ANDQ R12,R10
63 SUBQ R10,SI
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll89 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
92 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
97 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
120 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
123 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
128 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
151 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
[all …]
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s117 MOVW R10,#0x3311
118 VMOV.16 D0[0],R10 @//C1
120 MOVW R10,#0xF379
121 VMOV.16 D0[1],R10 @//C2
123 MOVW R10,#0xE5F8
124 VMOV.16 D0[2],R10 @//C3
126 MOVW R10,#0x4092
127 VMOV.16 D0[3],R10 @//C4
130 MOV R10,#128
131 VDUP.8 D1,R10
[all …]
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_amd64.s74 XORQ R10, R10 // h2
80 POLY1305_ADD(SI, R8, R9, R10)
83 POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
107 ADCQ $0, R10
116 SBBQ $3, R10
/external/llvm/test/CodeGen/Mips/
Datomic.ll145 ; O0: ld $[[R10:[0-9]+]]
146 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
190 ; O0: ld $[[R10:[0-9]+]]
191 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
235 ; O0: ld $[[R10:[0-9]+]]
236 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
281 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
283 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
DMSP430RegisterInfo.td59 def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td36 def RR1 : LanaiReg<10, "rr1", [R10]>, DwarfRegAlias<R10>;
51 R10, RR1, R11, RR2, // programmer controlled registers
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
86 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
429 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
436 ARM::R8, ARM::R10 in getRawAllocationOrder()
441 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
448 ARM::R8, ARM::R10 in getRawAllocationOrder()
454 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
459 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
465 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, in getRawAllocationOrder()
472 ARM::R10 in getRawAllocationOrder()
[all …]
DARMBaseRegisterInfo.h45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
/external/llvm/lib/Target/ARM/
DARMCallingConv.td27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
52 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
167 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
183 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
207 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
228 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
246 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
254 R11, R10, R9, R8,
261 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
DARMBaseRegisterInfo.h41 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
52 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreFrameLowering.cpp173 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); in emitPrologue()
175 MBB.addLiveIn(XCore::R10); in emitPrologue()
180 MachineLocation CSSrc(XCore::R10); in emitPrologue()
184 unsigned FramePtr = XCore::R10; in emitPrologue()
225 unsigned FramePtr = XCore::R10; in emitEpilogue()
251 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); in emitEpilogue()
DXCoreRegisterInfo.td36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
51 R4, R5, R6, R7, R8, R9, R10)>;
/external/llvm/lib/Target/BPF/
DBPFRegisterInfo.td32 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
40 R10 // frame ptr
DBPFRegisterInfo.cpp39 Reserved.set(BPF::R10); // R10 is read only frame pointer in getReservedRegs()
102 return BPF::R10; in getFrameRegister()
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Djumptable.ll49 %R10 = xor i32 %A, %B ; <i32> [#uses=1]
50 ret i32 %R10
/external/libunwind/src/x86_64/
Dinit.h59 c->dwarf.loc[R10] = REG_INIT_LOC(c, r10, R10); in common_init()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h115 case MBlaze::R10 : return 10; in getMBlazeRegisterNumbering()
180 case 10 : return MBlaze::R10; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, in initLLVMToSEHAndCVRegMapping()
325 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
362 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
398 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
434 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
435 return X86::R10; in getX86SubSuperRegisterOrZero()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td55 def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>;
101 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1

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