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Searched refs:R15 (Results 1 – 25 of 100) sorted by relevance

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/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_amd64.s65 MOVQ mlen+16(FP), R15
76 CMPQ R15, $16
84 SUBQ $16, R15
85 CMPQ R15, $16
89 TESTQ R15, R15
94 ADDQ R15, SI
102 DECQ R15
108 MOVQ $16, R15
/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s74 MOVQ DX,R15
88 ADCQ DX,R15
97 ADCQ DX,R15
135 SHLQ $13,R15:R14
138 IMUL3Q $19,R15,CX
189 MOVQ DX,R15
203 ADCQ DX,R15
212 ADCQ DX,R15
250 SHLQ $13,R15:R14
253 IMUL3Q $19,R15,CX
[all …]
Dsquare_amd64.s39 MOVQ AX,R15
53 ADDQ AX,R15
62 ADDQ AX,R15
101 SHLQ $13,BX:R15
102 ANDQ SI,R15
103 ADDQ R14,R15
120 ADDQ R15,DX
Dmul_amd64.s46 MOVQ DX,R15
62 ADCQ DX,R15
79 ADCQ DX,R15
97 ADCQ DX,R15
125 ADCQ DX,R15
135 SHLQ $13,R15:R14
140 ADDQ R15,BX
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
124 .addReg(Alpha::R15); in emitEpilogue()
126 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) in emitEpilogue()
127 .addImm(0).addReg(Alpha::R15); in emitEpilogue()
DAlphaRegisterInfo.cpp73 Reserved.set(Alpha::R15); in getReservedRegs()
149 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); in eliminateFrameIndex()
172 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); in eliminateFrameIndex()
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; in getFrameRegister()
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll97 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
98 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
128 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
129 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
160 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
161 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
189 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
190 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
220 ; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
221 ; CHECK: sc $[[R15]], 0($[[R2]])
[all …]
/external/llvm/test/CodeGen/X86/
Dipra-local-linkage.ll7 ; When IPRA is not enabled R15 will be saved by foo as it is callee saved reg.
20 ; As R15 is clobbered by foo() when IPRA is enabled value of R15 should be
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td38 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
50 R15, RCA, // register for constant addresses
/external/llvm/test/CodeGen/Mips/
Datomic.ll152 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
197 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
242 ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
244 ; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]]
290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
291 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
332 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
DMSP430RegisterInfo.td64 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp86 case X86::ESI: case X86::R15: return 5; in getCompactUnwindRegNum()
104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: in getSEHRegNum()
361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
366 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
371 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
433 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
711 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
748 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
784 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
820 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegister()
[all …]
/external/libunwind/src/x86_64/
Dinit.h64 c->dwarf.loc[R15] = REG_INIT_LOC(c, r15, R15); in common_init()
Dunwind_i.h54 #define R15 15 macro
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h120 case MBlaze::R15 : return 15; in getMBlazeRegisterNumbering()
185 case 15 : return MBlaze::R15; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp111 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, in initLLVMToSEHAndCVRegMapping()
335 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
372 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
408 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
444 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
445 return X86::R15; in getX86SubSuperRegisterOrZero()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td60 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
99 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp46 : MBlazeGenRegisterInfo(MBlaze::R15), Subtarget(ST), TII(tii) {} in MBlazeRegisterInfo()
78 Reserved.set(MBlaze::R15); in getReservedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
/external/strace/linux/x86_64/
Duserent.h1 XLAT(8*R15),
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h170 {PPC::R15, -68}, in getCalleeSavedSpillSlots()
249 {PPC::R15, -132}, in getCalleeSavedSpillSlots()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h32 #define R15 0 macro
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h8 #define R15 r15 macro

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