| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_vec.c | 65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
161 p->R20.d[1] = (uint32_t)(r0); in CRYPTO_poly1305_init()
162 p->R20.d[3] = (uint32_t)(r0 >> 32); in CRYPTO_poly1305_init()
202 r0 = ((uint64_t)p->R20.d[3] << 32) | (uint64_t)p->R20.d[1]; in poly1305_first_block()
232 p->R20.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)(r20)&0x3ffffff), in poly1305_first_block()
254 p->R20.d[1] = (uint32_t)(r0); in poly1305_first_block()
255 p->R20.d[3] = (uint32_t)(r0 >> 32); in poly1305_first_block()
299 T0 = _mm_mul_epu32(H0, p->R20.v); in poly1305_blocks()
305 T6 = _mm_mul_epu32(H1, p->R20.v); in poly1305_blocks()
324 T5 = _mm_mul_epu32(H2, p->R20.v); in poly1305_blocks()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaCallingConv.td | 30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
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| D | AlphaRegisterInfo.td | 58 def R20 : GPR<20, "$20">, DwarfRegNum<[20]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 65 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
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| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 125 case MBlaze::R20 : return 20; in getMBlazeRegisterNumbering()
190 case 20 : return MBlaze::R20; in getMBlazeRegisterFromNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 49 return MBlaze::R20; in getPICCallReg()
61 MBlaze::R20, MBlaze::R21, MBlaze::R22, MBlaze::R23, in getCalleeSavedRegs()
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| D | MBlazeInstrInfo.cpp | 292 GlobalBaseReg).addReg(MBlaze::R20); in getGlobalBaseReg()
293 RegInfo.addLiveIn(MBlaze::R20); in getGlobalBaseReg()
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| D | MBlazeISelDAGToDAG.cpp | 228 SDValue R20Reg = CurDAG->getRegister(MBlaze::R20, MVT::i32); in Select()
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| D | MBlazeRegisterInfo.td | 62 def R20 : MBlazeGPRReg< 20, "r20">, DwarfRegNum<[20]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
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| D | SPURegisterInfo.cpp | 74 case SPU::R20: return 20; in getRegisterNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 165 {PPC::R20, -48}, in getCalleeSavedSpillSlots()
244 {PPC::R20, -92}, in getCalleeSavedSpillSlots()
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| D | PPCRegisterInfo.td | 88 def R20 : GPR<20, "r20">, DwarfRegNum<[-2, 20]>;
122 def X20 : GP8<R20, "r20">, DwarfRegNum<[20, -2]>;
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| D | PPCRegisterInfo.cpp | 108 PPC::R20, PPC::R21, PPC::R22, PPC::R23, in getCalleeSavedRegs()
134 PPC::R20, PPC::R21, PPC::R22, PPC::R23, in getCalleeSavedRegs()
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| /external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
| D | ppc_asm.h | 13 #define R20 r20 macro
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 90 case Lanai::R20: in getLanaiRegisterNumbering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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| D | HexagonFrameLowering.h | 65 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
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| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 253 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
254 ; NO-SEB-SEH: sra $2, $[[R20]], 24
390 ; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24
391 ; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24
396 ; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 51 case R20: case X20: case F20: case V20: case CR5LT: return 20; in getPPCRegisterNumbering()
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| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
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| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 222 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
231 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 169 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
|