| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_vec.c | 65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
163 p->R21.d[1] = (uint32_t)(r1); in CRYPTO_poly1305_init()
164 p->R21.d[3] = (uint32_t)(r1 >> 32); in CRYPTO_poly1305_init()
203 r1 = ((uint64_t)p->R21.d[3] << 32) | (uint64_t)p->R21.d[1]; in poly1305_first_block()
234 p->R21.v = _mm_shuffle_epi32( in poly1305_first_block()
245 p->S21.v = _mm_mul_epu32(p->R21.v, FIVE); in poly1305_first_block()
256 p->R21.d[1] = (uint32_t)(r1); in poly1305_first_block()
257 p->R21.d[3] = (uint32_t)(r1 >> 32); in poly1305_first_block()
300 T1 = _mm_mul_epu32(H0, p->R21.v); in poly1305_blocks()
320 T5 = _mm_mul_epu32(H1, p->R21.v); in poly1305_blocks()
[all …]
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| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 14 branch_points: R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22,
27 # Note that the builders have produced R21 tagged artifacts beginning 2266.0.0
30 # R21 actual branchpoint is 2465.0.0
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaCallingConv.td | 30 CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
34 [R16, R17, R18, R19, R20, R21]>>,
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| D | AlphaRegisterInfo.td | 59 def R21 : GPR<21, "$21">, DwarfRegNum<[21]>;
115 R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 66 def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>;
96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
147 add R23, R22, R21, R20, R19, R18, R17, R16
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| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 126 case MBlaze::R21 : return 21; in getMBlazeRegisterNumbering()
191 case 21 : return MBlaze::R21; in getMBlazeRegisterFromNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
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| D | SPURegisterInfo.cpp | 75 case SPU::R21: return 21; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 45 def R21 : SPUVecReg<21, "$21">, DwarfRegNum<[21]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 164 {PPC::R21, -44}, in getCalleeSavedSpillSlots()
243 {PPC::R21, -84}, in getCalleeSavedSpillSlots()
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| D | PPCRegisterInfo.td | 89 def R21 : GPR<21, "r21">, DwarfRegNum<[-2, 21]>;
123 def X21 : GP8<R21, "r21">, DwarfRegNum<[21, -2]>;
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| D | PPCRegisterInfo.cpp | 108 PPC::R20, PPC::R21, PPC::R22, PPC::R23, in getCalleeSavedRegs()
134 PPC::R20, PPC::R21, PPC::R22, PPC::R23, in getCalleeSavedRegs()
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| /external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/ |
| D | ppc_asm.h | 14 #define R21 r21 macro
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 92 case Lanai::R21: in getLanaiRegisterNumbering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
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| D | HexagonFrameLowering.h | 65 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 52 case R21: case X21: case F21: case V21: case CR5GT: return 21; in getPPCRegisterNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 61 MBlaze::R20, MBlaze::R21, MBlaze::R22, MBlaze::R23, in getCalleeSavedRegs()
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| D | MBlazeRegisterInfo.td | 63 def R21 : MBlazeGPRReg< 21, "r21">, DwarfRegNum<[21]>;
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| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 159 Lanai::R18, Lanai::R19, Lanai::R20, Lanai::R21, Lanai::R22, Lanai::R23,
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| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 396 ; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]]
397 ; HAS-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $5
399 ; ALL: sltiu $2, $[[R21]], 1
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 169 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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| /external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
| D | DebugSupport.h | 310 UINT64 R21; member
|