| /external/llvm/lib/Target/AVR/ |
| D | AVRCallingConv.td | 18 // i8 is returned in R24.
19 CCIfType<[i8], CCAssignToReg<[R24]>>,
21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
28 CCIfType<[i8], CCAssignToReg<[R24,R25]>>,
56 CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
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| D | AVRRegisterInfo.td | 69 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
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| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_vec.c | 65 } R20, R21, R22, R23, R24, S21, S22, S23, S24; member
171 p->R24.d[1] = U8TO32_LE(key + 24); in CRYPTO_poly1305_init()
172 p->R24.d[3] = U8TO32_LE(key + 28); in CRYPTO_poly1305_init()
206 pad1 = ((uint64_t)p->R24.d[3] << 32) | (uint64_t)p->R24.d[1]; in poly1305_first_block()
243 p->R24.v = _mm_shuffle_epi32(_mm_cvtsi32_si128((uint32_t)((r22 >> 16))), in poly1305_first_block()
248 p->S24.v = _mm_mul_epu32(p->R24.v, FIVE); in poly1305_first_block()
262 p->R24.d[1] = (uint32_t)(pad1); in poly1305_first_block()
263 p->R24.d[3] = (uint32_t)(pad1 >> 32); in poly1305_first_block()
303 T4 = _mm_mul_epu32(H0, p->R24.v); in poly1305_blocks()
398 T5 = _mm_mul_epu32(M0, p->R24.v); in poly1305_blocks()
[all …]
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 15 R23, R24, R25, R26, R27, R28, R29, R30, R31
36 # R24 is not a real branchpoint, since the branch was skipped. The first
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 129 case MBlaze::R24 : return 24; in getMBlazeRegisterNumbering()
194 case 24 : return MBlaze::R24; in getMBlazeRegisterFromNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
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| D | SPURegisterInfo.cpp | 78 case SPU::R24: return 24; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 48 def R24 : SPUVecReg<24, "$24">, DwarfRegNum<[24]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 161 {PPC::R24, -32}, in getCalleeSavedSpillSlots()
240 {PPC::R24, -60}, in getCalleeSavedSpillSlots()
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| D | PPCRegisterInfo.td | 92 def R24 : GPR<24, "r24">, DwarfRegNum<[-2, 24]>;
126 def X24 : GP8<R24, "r24">, DwarfRegNum<[24, -2]>;
|
| D | PPCRegisterInfo.cpp | 109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 98 case Lanai::R24: in getLanaiRegisterNumbering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
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| D | HexagonFrameLowering.h | 67 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, in getCalleeSavedSpillSlots()
|
| D | HexagonRegisterInfo.td | 111 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 62 def R24 : GPR<24, "$24">, DwarfRegNum<[24]>;
116 R23, R24, R25, R28,
|
| D | AlphaISelDAGToDAG.cpp | 235 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1, in Select()
|
| D | AlphaInstrInfo.td | 405 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
413 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
421 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 55 case R24: case X24: case F24: case V24: case CR6LT: return 24; in getPPCRegisterNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
|
| D | MBlazeRegisterInfo.td | 66 def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>;
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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| /external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
| D | DebugSupport.h | 313 UINT64 R24; member
|