| /external/llvm/lib/Target/AVR/ |
| D | AVRCallingConv.td | 21 // i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
28 CCIfType<[i8], CCAssignToReg<[R24,R25]>>,
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| D | AVRRegisterInfo.td | 70 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
119 add R24, R25, R18, R19, R20, R21, R22, R23,
137 add R24, R25, R18, R19, R20, R21, R22, R23,
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| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 15 R23, R24, R25, R26, R27, R28, R29, R30, R31
39 # R25 actual branchpoint is 3428.0.0
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 130 case MBlaze::R25 : return 25; in getMBlazeRegisterNumbering()
195 case 25 : return MBlaze::R25; in getMBlazeRegisterFromNumbering()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
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| D | SPURegisterInfo.cpp | 79 case SPU::R25: return 25; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 49 def R25 : SPUVecReg<25, "$25">, DwarfRegNum<[25]>;
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 160 {PPC::R25, -28}, in getCalleeSavedSpillSlots()
239 {PPC::R25, -52}, in getCalleeSavedSpillSlots()
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| D | PPCRegisterInfo.td | 93 def R25 : GPR<25, "r25">, DwarfRegNum<[-2, 25]>;
127 def X25 : GP8<R25, "r25">, DwarfRegNum<[25, -2]>;
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| D | PPCRegisterInfo.cpp | 109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 100 case Lanai::R25: in getLanaiRegisterNumbering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
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| D | HexagonFrameLowering.h | 67 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, in getCalleeSavedSpillSlots()
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| D | HexagonRegisterInfo.td | 111 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
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| D | HexagonFrameLowering.cpp | 779 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26, in insertCFIInstructionsAt()
948 case Hexagon::R25: in getSpillFunctionFor()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 63 def R25 : GPR<25, "$25">, DwarfRegNum<[25]>;
116 R23, R24, R25, R28,
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| D | AlphaISelDAGToDAG.cpp | 237 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2, in Select()
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| D | AlphaInstrInfo.td | 405 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
413 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
421 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 56 case R25: case X25: case F25: case V25: case CR6GT: return 25; in getPPCRegisterNumbering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
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| D | MBlazeRegisterInfo.td | 67 def R25 : MBlazeGPRReg< 25, "r25">, DwarfRegNum<[25]>;
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| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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| /external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
| D | DebugSupport.h | 314 UINT64 R25; member
|