| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| D | MBlazeBaseInfo.h | 131 case MBlaze::R26 : return 26; in getMBlazeRegisterNumbering()
196 case 26 : return MBlaze::R26; in getMBlazeRegisterFromNumbering()
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 71 def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>;
92 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
|
| D | SPURegisterInfo.cpp | 80 case SPU::R26: return 26; in getRegisterNumbering()
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| D | SPURegisterInfo.td | 50 def R26 : SPUVecReg<26, "$26">, DwarfRegNum<[26]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.h | 159 {PPC::R26, -24}, in getCalleeSavedSpillSlots()
238 {PPC::R26, -44}, in getCalleeSavedSpillSlots()
|
| D | PPCRegisterInfo.td | 94 def R26 : GPR<26, "r26">, DwarfRegNum<[-2, 26]>;
128 def X26 : GP8<R26, "r26">, DwarfRegNum<[26, -2]>;
|
| D | PPCRegisterInfo.cpp | 109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/MCTargetDesc/ |
| D | AlphaMCTargetDesc.cpp | 42 InitAlphaMCRegisterInfo(X, Alpha::R26); in createAlphaMCRegisterInfo()
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiBaseInfo.h | 102 case Lanai::R26: in getLanaiRegisterNumbering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
|
| D | HexagonFrameLowering.h | 68 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } in getCalleeSavedSpillSlots()
|
| D | HexagonRegisterInfo.td | 112 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaRegisterInfo.td | 64 def R26 : GPR<26, "$26">, DwarfRegNum<[26]>;
119 R26, //return address
|
| D | AlphaInstrInfo.cpp | 377 GlobalRetAddr).addReg(Alpha::R26); in getGlobalRetAddr()
378 RegInfo.addLiveIn(Alpha::R26); in getGlobalRetAddr()
|
| D | AlphaRegisterInfo.cpp | 42 : AlphaGenRegisterInfo(Alpha::R26), TII(tii) { in AlphaRegisterInfo()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 57 case R26: case X26: case F26: case V26: case CR6EQ: return 26; in getPPCRegisterNumbering()
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 15 R23, R24, R25, R26, R27, R28, R29, R30, R31
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
|
| D | MBlazeRegisterInfo.td | 68 def R26 : MBlazeGPRReg< 26, "r26">, DwarfRegNum<[26]>;
|
| /external/python/cpython2/Lib/test/ |
| D | sha256.pem | 95 rVE04BKT6b64q7gmtOmWPSiPrmQH/uAB7MXjkesYoPF1ftsK5p+R26+udd8jkWjd
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
|
| /external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
| D | DebugSupport.h | 315 UINT64 R26; member
|