/external/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg() 109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs() 118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
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D | HexagonFrameLowering.h | 68 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } in getCalleeSavedSpillSlots()
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D | HexagonRegisterInfo.td | 112 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
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D | HexagonFrameLowering.cpp | 779 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26, in insertCFIInstructionsAt() 950 case Hexagon::R27: in getSpillFunctionFor()
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
D | MBlazeBaseInfo.h | 132 case MBlaze::R27 : return 27; in getMBlazeRegisterNumbering() 197 case 27 : return MBlaze::R27; in getMBlazeRegisterFromNumbering()
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/external/llvm/lib/Target/AVR/ |
D | AVRRegisterInfo.td | 72 def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>; 92 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>; 121 R30, R31, R26, R27, 139 R30, R31, R26, R27,
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPUCallingConv.td | 27 R21, R22, R23, R24, R25, R26, R27, R28, R29, 44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
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D | SPURegisterInfo.cpp | 81 case SPU::R27: return 27; in getRegisterNumbering()
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D | SPURegisterInfo.td | 51 def R27 : SPUVecReg<27, "$27">, DwarfRegNum<[27]>;
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCFrameLowering.h | 158 {PPC::R27, -20}, in getCalleeSavedSpillSlots() 237 {PPC::R27, -36}, in getCalleeSavedSpillSlots()
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D | PPCRegisterInfo.td | 95 def R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>; 129 def X27 : GP8<R27, "r27">, DwarfRegNum<[27, -2]>;
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D | PPCRegisterInfo.cpp | 109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs() 135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
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/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
D | LanaiBaseInfo.h | 104 case Lanai::R27: in getLanaiRegisterNumbering()
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaISelDAGToDAG.cpp | 239 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, in Select() 244 Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, in Select() 408 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); in SelectCALL()
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D | AlphaRegisterInfo.td | 65 def R27 : GPR<27, "$27">, DwarfRegNum<[27]>; 118 R27, //procedure address
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D | AlphaFrameLowering.cpp | 57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); in emitPrologue()
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D | AlphaInstrInfo.td | 405 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, 413 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, 416 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in { 421 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
D | PPCBaseInfo.h | 58 case R27: case X27: case F27: case V27: case CR6UN: return 27; in getPPCRegisterNumbering()
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/external/autotest/site_utils/autoupdate/ |
D | release_config.ini | 15 R23, R24, R25, R26, R27, R28, R29, R30, R31
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeRegisterInfo.cpp | 62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
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D | MBlazeRegisterInfo.td | 69 def R27 : MBlazeGPRReg< 27, "r27">, DwarfRegNum<[27]>;
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/external/llvm/lib/Target/Lanai/Disassembler/ |
D | LanaiDisassembler.cpp | 160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
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/external/llvm/lib/Target/PowerPC/ |
D | PPCCallingConv.td | 223 R21, R22, R23, R24, R25, R26, R27, R28, 232 R21, R22, R23, R24, R25, R26, R27, R28,
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/external/llvm/lib/Target/PowerPC/Disassembler/ |
D | PPCDisassembler.cpp | 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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/external/syslinux/gpxe/src/include/gpxe/efi/Protocol/ |
D | DebugSupport.h | 316 UINT64 R27; member
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