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Searched refs:R27 (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg()
109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
DHexagonFrameLowering.h68 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } in getCalleeSavedSpillSlots()
DHexagonRegisterInfo.td112 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
DHexagonFrameLowering.cpp779 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26, in insertCFIInstructionsAt()
950 case Hexagon::R27: in getSpillFunctionFor()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h132 case MBlaze::R27 : return 27; in getMBlazeRegisterNumbering()
197 case 27 : return MBlaze::R27; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td72 def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>;
92 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td27 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R21, R22, R23, R24, R25, R26, R27, R28, R29,
DSPURegisterInfo.cpp81 case SPU::R27: return 27; in getRegisterNumbering()
DSPURegisterInfo.td51 def R27 : SPUVecReg<27, "$27">, DwarfRegNum<[27]>;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h158 {PPC::R27, -20}, in getCalleeSavedSpillSlots()
237 {PPC::R27, -36}, in getCalleeSavedSpillSlots()
DPPCRegisterInfo.td95 def R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>;
129 def X27 : GP8<R27, "r27">, DwarfRegNum<[27, -2]>;
DPPCRegisterInfo.cpp109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, in getCalleeSavedRegs()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h104 case Lanai::R27: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelDAGToDAG.cpp239 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, in Select()
244 Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, in Select()
408 Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); in SelectCALL()
DAlphaRegisterInfo.td65 def R27 : GPR<27, "$27">, DwarfRegNum<[27]>;
118 R27, //procedure address
DAlphaFrameLowering.cpp57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); in emitPrologue()
DAlphaInstrInfo.td405 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
413 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
416 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
421 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h58 case R27: case X27: case F27: case V27: case CR6UN: return 27; in getPPCRegisterNumbering()
/external/autotest/site_utils/autoupdate/
Drelease_config.ini15 R23, R24, R25, R26, R27, R28, R29, R30, R31
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp62 MBlaze::R24, MBlaze::R25, MBlaze::R26, MBlaze::R27, in getCalleeSavedRegs()
DMBlazeRegisterInfo.td69 def R27 : MBlazeGPRReg< 27, "r27">, DwarfRegNum<[27]>;
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td223 R21, R22, R23, R24, R25, R26, R27, R28,
232 R21, R22, R23, R24, R25, R26, R27, R28,
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp170 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
/external/syslinux/gpxe/src/include/gpxe/efi/Protocol/
DDebugSupport.h316 UINT64 R27; member

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