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Searched refs:R30 (Results 1 – 25 of 42) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaFrameLowering.cpp82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitPrologue()
83 .addReg(Alpha::R30); in emitPrologue()
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) in emitPrologue()
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) in emitPrologue()
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30); in emitPrologue()
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); in emitPrologue()
99 .addReg(Alpha::R30).addReg(Alpha::R30); in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) in emitEpilogue()
132 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) in emitEpilogue()
[all …]
DAlphaRegisterInfo.cpp75 Reserved.set(Alpha::R30); in getReservedRegs()
104 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) in eliminateCallFramePseudoInstr()
105 .addImm(-Amount).addReg(Alpha::R30); in eliminateCallFramePseudoInstr()
108 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) in eliminateCallFramePseudoInstr()
109 .addImm(Amount).addReg(Alpha::R30); in eliminateCallFramePseudoInstr()
149 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); in eliminateFrameIndex()
172 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); in eliminateFrameIndex()
182 return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; in getFrameRegister()
DAlphaRegisterInfo.td68 def R30 : GPR<30, "$30">, DwarfRegNum<[30]>;
124 R15, R30, R31)>; //zero
DAlphaLLRP.cpp70 if (MI->getOperand(2).getReg() == Alpha::R30) { in runOnMachineFunction()
/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
696 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
706 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
DHexagonRegisterInfo.cpp140 Reserved.set(Hexagon::R30); in getReservedRegs()
228 return Hexagon::R30; in getFrameRegister()
DHexagonRegisterInfo.td94 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
114 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
215 R10, R11, R29, R30, R31)> {
/external/llvm/test/CodeGen/Hexagon/
Dcfi-offset.ll3 ; They are all based on R30+8 which points to the pair FP/LR stored by an
6 ; R30+8.
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h135 case MBlaze::R30 : return 30; in getMBlazeRegisterNumbering()
200 case 30 : return MBlaze::R30; in getMBlazeRegisterFromNumbering()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td75 def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td28 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R30, R31, R32, R33, R34, R35, R36, R37, R38,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h155 {PPC::R30, -8}, in getCalleeSavedSpillSlots()
234 {PPC::R30, -12}, in getCalleeSavedSpillSlots()
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h17 #define R30 r30 macro
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h110 case Lanai::R30: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCBaseInfo.h61 case R30: case X30: case F30: case V30: case CR7EQ: return 30; in getPPCRegisterNumbering()
/external/autotest/site_utils/autoupdate/
Drelease_config.ini15 R23, R24, R25, R26, R27, R28, R29, R30, R31
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.cpp63 MBlaze::R28, MBlaze::R29, MBlaze::R30, MBlaze::R31, in getCalleeSavedRegs()
DMBlazeRegisterInfo.td72 def R30 : MBlazeGPRReg< 30, "r30">, DwarfRegNum<[30]>;
/external/autotest/server/site_tests/autoupdate_EndToEndTest/
Dcontrol75 gs://chromeos-image-archive/lumpy-release/R30-4462.0.0/
79 gs://chromeos-image-archive/lumpy-release/R30-4463.0.0/
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCTargetDesc.cpp195 MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); in createHexagonMCAsmInfo()
/external/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp161 Lanai::R30, Lanai::R31};
/external/autotest/
Dglobal_config.ini340 RELEASED_RO_BUILDS_wolf: wolf-firmware/R30-4389.24.62,wolf-firmware/R30-4389.24.58,wolf-firmware/R3…
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp268 Reserved.set(PPC::R30); in getReservedRegs()
272 Reserved.set(PPC::R30); in getReservedRegs()
940 return PPC::R30; in getBaseRegister()
DPPCCallingConv.td224 R29, R30, R31, F14, F15, F16, F17, F18,
233 R29, R30, R31, F14, F15, F16, F17, F18,
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp171 PPC::R28, PPC::R29, PPC::R30, PPC::R31
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31

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