| /external/swiftshader/third_party/LLVM/test/TableGen/ |
| D | Tree.td | 11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
|
| D | TreeNames.td | 11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
|
| D | TargetInstrInfo.td | 37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
|
| /external/llvm/test/TableGen/ |
| D | Tree.td | 11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32, R32))>; // a = b + c
18 def ADDri32 : Inst<(set R32, (plus R32, imm))>; // a = b + imm
|
| D | TreeNames.td | 11 def R32 : RegisterClass;
17 def ADDrr32 : Inst<(set R32, (plus R32:$A, R32:$def))>;
|
| D | TargetInstrInfo.td | 37 def R32 : RegisterClass;
108 def SHL32rCL : Inst<(ops R32:$dst, R32:$src),
110 [(set R32:$dst, (shl R32:$src, CL))]>;
117 [(set R32:$tmp1, (load addr:$addr)),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
119 (store addr:$addr, R32:$tmp2)]>;
126 def AND32mr : Inst<(ops addr:$addr, R32:$src),
131 R32:$src)
|
| /external/python/cpython2/Modules/ |
| D | shamodule.c | 130 #define R32(x,n) ((x << n) | (x >> (32 - n))) macro
135 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; \
136 E = D; D = C; C = R32(B,30); B = A; A = T
141 T = R32(A,5) + f##n(B,C,D) + E + *WP++ + CONST##n; B = R32(B,30)
144 E = R32(T,5) + f##n(A,B,C) + D + *WP++ + CONST##n; A = R32(A,30)
147 D = R32(E,5) + f##n(T,A,B) + C + *WP++ + CONST##n; T = R32(T,30)
150 C = R32(D,5) + f##n(E,T,A) + B + *WP++ + CONST##n; E = R32(E,30)
153 B = R32(C,5) + f##n(D,E,T) + A + *WP++ + CONST##n; D = R32(D,30)
156 A = R32(B,5) + f##n(C,D,E) + T + *WP++ + CONST##n; C = R32(C,30)
173 W[i] = R32(W[i], 1); in sha_transform()
|
| /external/autotest/server/site_tests/autoupdate_Rollback/ |
| D | control | 36 gs://chromeos-image-archive/parrot-release/R32-4793.0.0&\
40 parrot-release/R32-4793.0.0/autotest/packages"
45 parrot-release/R32-4793.0.0/autotest/packages" --fast \
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_formats.c | 174 F3(A, L32_FLOAT, R32_FLOAT, R, R, R, xx, FLOAT, R32, TB),
175 I3(A, L32_SINT, R32_SINT, R, R, R, xx, SINT, R32, TR),
176 I3(A, L32_UINT, R32_UINT, R, R, R, xx, UINT, R32, TR),
187 C4(A, I32_FLOAT, R32_FLOAT, R, R, R, R, FLOAT, R32, TR),
188 C4(A, I32_SINT, R32_SINT, R, R, R, R, SINT, R32, TR),
189 C4(A, I32_UINT, R32_UINT, R, R, R, R, UINT, R32, TR),
200 A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, R, FLOAT, R32, T),
201 A1(A, A32_SINT, R32_SINT, xx, xx, xx, R, SINT, R32, T),
202 A1(A, A32_UINT, R32_UINT, xx, xx, xx, R, UINT, R32, T),
305 F1(A, R32_FLOAT, R32_FLOAT, R, xx, xx, xx, FLOAT, R32, IB),
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUCallingConv.td | 28 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R30, R31, R32, R33, R34, R35, R36, R37, R38,
|
| D | SPURegisterInfo.cpp | 86 case SPU::R32: return 32; in getRegisterNumbering()
|
| D | SPURegisterInfo.td | 56 def R32 : SPUVecReg<32, "$32">, DwarfRegNum<[32]>;
|
| D | SPUISelLowering.cpp | 1206 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37, in LowerFormalArguments()
|
| D | SPUInstrInfo.td | 3414 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | 2006-05-08-CoalesceSubRegClass.ll | 1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
|
| /external/llvm/test/CodeGen/X86/ |
| D | 2006-05-08-CoalesceSubRegClass.ll | 1 ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
|
| /external/autotest/site_utils/autoupdate/ |
| D | release_config.ini | 47 next_branch: R32
|
| /external/autotest/docs/ |
| D | test-that.md | 98 test_that -b peach_pit :lab: suite:pyauto_perf -i 'peach_pit-release/R32-4763.0.0'
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 1383 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass; in generateInserts() local
1384 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert) in generateInserts()
1389 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) { in generateInserts()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | Target.td | 427 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
|
| /external/llvm/include/llvm/Target/ |
| D | Target.td | 541 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
|
| /external/autotest/ |
| D | global_config.ini | 329 RELEASED_RO_BUILDS_panther: panther-firmware/R32-4920.24.26
|
| /external/lisa/ipynb/sched_tune/ |
| D | stune_juno_rampL.ipynb | 337 …oSHyJ//JjPYctmTy0yuEEAZTVOR8HVIhhHClcms5m49sZlyfcTwx\n5ImK/ZuPbMaiWzwWx+mJ/R32+bSkv2JDD3PKHBNzdsyi…
|