Home
last modified time | relevance | path

Searched refs:R5 (Results 1 – 25 of 164) sorted by relevance

1234567

/external/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
6 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
8 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
10 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
16 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
18 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
20 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
22 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
41 ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
42 ; 32R1-R5: sll $[[T0]], $[[T0]], 31
[all …]
Durem.ll6 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
8 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
10 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
21 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
23 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
25 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
88 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
89 ; R2-R5: teq $[[T0]], $zero, 7
[all …]
Dsrem.ll6 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
8 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
10 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
21 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
23 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
25 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
76 ; R2-R5: div $zero, $4, $5
77 ; R2-R5: teq $5, $zero, 7
78 ; R2-R5: mfhi $[[T0:[0-9]+]]
79 ; R2-R5: seb $2, $[[T0]]
[all …]
Dashr.ll4 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
101 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
102 ; 32R1-R5: not $[[T1:[0-9]+]], $7
103 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
104 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
105 ; 32R1-R5: or $3, $[[T3]], $[[T0]]
106 ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7
[all …]
Dsdiv.ll6 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
8 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
10 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
21 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
23 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
25 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
79 ; R2-R5: div $zero, $4, $5
80 ; R2-R5: teq $5, $zero, 7
81 ; R2-R5: mflo $[[T0:[0-9]+]]
83 ; R2-R5: seb $2, $[[T0]]
[all …]
Dlshr.ll4 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
99 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
100 ; 32R1-R5: not $[[T1:[0-9]+]], $7
101 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
102 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
103 ; 32R1-R5: or $3, $[[T3]], $[[T0]]
104 ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
[all …]
Dshl.ll4 ; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
115 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
116 ; 32R1-R5: not $[[T1:[0-9]+]], $7
117 ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1
118 ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
119 ; 32R1-R5: or $2, $[[T0]], $[[T3]]
120 ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7
[all …]
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_arm.s29 MOVM.IA.W (R1), [R2-R5]
35 MOVW R5>>8, R12
38 ORR R5<<18, R11, R11
43 AND R11, R5, R5
49 EOR R5, R5, R5
52 MOVM.IA.W (R1), [R2-R5]
122 ADD R0, R5, R5
130 MULLU R4, R5, (R11, g)
131 MULLU R3, R5, (R14, R12)
146 MULLU R2, R5, (R11, g)
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll137 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
138 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
160 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
181 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
183 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
205 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
[all …]
Dcttz-v.ll14 ; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1
16 ; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
29 ; MIPS64-DAG: addiu $[[R5:[0-9]+]], $[[A1]], -1
31 ; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
D2010-07-20-Switch.ll27 ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
28 ; PIC-O32: jr $[[R5]]
33 ; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
34 ; N64: jr $[[R5]]
Dcountleading.ll60 ; MIPS32-R6-DAG: seleqz $[[R5:[0-9]+]], $[[R2]], $5
62 ; MIPS32-R6-DAG: or $2, $[[R6]], $[[R5]]
86 ; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
88 ; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll83 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
84 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
114 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
115 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
145 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
146 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
177 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
178 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
206 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
207 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
/external/icu/icu4c/source/data/mappings/
Dlmb-excp.ucm33 <U005E> \x01\x33 |3 # R5 compatibility
34 <U005E> \x01\x6D |3 # R5 compatibility
36 <U0060> \x01\x34 |3 # R5 compatibility
38 <U007E> \x01\x31 |3 # R5 compatibility
39 <U007E> \x01\x6C |3 # R5 compatibility
43 <U00A8> \x01\x30 |3 # R5 compatibility
46 <U00B4> \x01\x35 |3 # R5 compatibility
115 <U02DA> \x01\x32 |3 # R5 compatibility
116 <U02DA> \x01\x44 |3 # R5 compatibility
/external/llvm/test/CodeGen/Mips/msa/
Di5-b.ll105 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)(
106 ; CHECK-DAG: st.b [[R3]], 0([[R5]])
130 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_h_RES)(
131 ; CHECK-DAG: st.h [[R3]], 0([[R5]])
155 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_w_RES)(
156 ; CHECK-DAG: st.w [[R3]], 0([[R5]])
184 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_d_RES)(
185 ; CHECK-DAG: st.d [[R3]], 0([[R5]])
209 ; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)(
210 ; CHECK-DAG: st.b [[R3]], 0([[R5]])
[all …]
Dvec.ll188 ; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
190 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
218 ; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
220 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
248 ; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
250 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
278 ; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
280 ; ANYENDIAN-DAG: bmnz.v [[R4]], [[R5]], [[R6]]
308 ; ANYENDIAN-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
311 ; ANYENDIAN-DAG: bmnz.v [[R5]], [[R4]], [[R6]]
[all …]
Dbasic_operations.ll206 ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp)
207 ; MIPS32-DAG: insert.b [[R1]][7], [[R5]]
208 ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]]
209 ; ALL-DAG: insert.b [[R1]][8], [[R5]]
210 ; ALL-DAG: insert.b [[R1]][9], [[R5]]
211 ; ALL-DAG: insert.b [[R1]][10], [[R5]]
212 ; ALL-DAG: insert.b [[R1]][11], [[R5]]
213 ; ALL-DAG: insert.b [[R1]][12], [[R5]]
214 ; ALL-DAG: insert.b [[R1]][13], [[R5]]
215 ; ALL-DAG: insert.b [[R1]][14], [[R5]]
[all …]
D3r-b.ll117 ; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
119 ; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]]
145 ; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]])
147 ; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]]
173 ; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]])
175 ; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]]
201 ; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]])
203 ; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]]
229 ; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
231 ; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp43 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
48 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
53 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
59 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td34 def FP : LanaiReg< 5, "fp", [R5]>, DwarfRegAlias<R5>;
53 R5, FP, // frame pointer
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp75 ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
85 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
430 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
434 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, in getRawAllocationOrder()
442 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, in getRawAllocationOrder()
446 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, in getRawAllocationOrder()
454 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
458 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, in getRawAllocationOrder()
466 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, in getRawAllocationOrder()
470 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, in getRawAllocationOrder()
[all …]
/external/icu/android_icu4j/src/main/java/android/icu/impl/
DRow.java38 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
39 return new R5<C0,C1,C2,C3,C4>(p0,p1,p2,p3,p4); in of()
57 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
58 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/external/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/
DRow.java34 public static <C0, C1, C2, C3, C4> R5<C0,C1,C2,C3,C4> of(C0 p0, C1 p1, C2 p2, C3 p3, C4 p4) { in of()
35 return new R5<C0,C1,C2,C3,C4>(p0,p1,p2,p3,p4); in of()
53 public static class R5<C0, C1, C2, C3, C4> extends Row<C0, C1, C2, C3, C4> { class in Row
54 public R5(C0 a, C1 b, C2 c, C3 d, C4 e) { in R5() method in Row.R5
/external/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td20 CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,
30 CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>,

1234567