| /external/llvm/include/llvm/ADT/ |
| D | SparseBitVector.h | 232 void intersectWithComplement(const SparseBitVectorElement &RHS1,
239 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
697 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
700 if (this == &RHS1) {
705 intersectWithComplement(RHS1, RHS2Copy);
711 ElementListConstIter Iter1 = RHS1.Elements.begin();
716 if (RHS1.Elements.empty())
721 if (Iter1 == RHS1.Elements.end())
747 while (Iter1 != RHS1.Elements.end()) {
755 void intersectWithComplement(const SparseBitVector<ElementSize> *RHS1,
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| /external/swiftshader/third_party/LLVM/include/llvm/ADT/ |
| D | SparseBitVector.h | 254 void intersectWithComplement(const SparseBitVectorElement &RHS1,
261 Bits[i] = RHS1.Bits[i] & ~RHS2.Bits[i];
691 void intersectWithComplement(const SparseBitVector<ElementSize> &RHS1,
696 ElementListConstIter Iter1 = RHS1.Elements.begin();
701 if (RHS1.Elements.empty())
706 if (Iter1 == RHS1.Elements.end())
732 while (Iter1 != RHS1.Elements.end()) {
742 void intersectWithComplement(const SparseBitVector<ElementSize> *RHS1,
744 intersectWithComplement(*RHS1, *RHS2);
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | GuardWidening.cpp | 410 ConstantInt *RHS0, *RHS1; in widenCondCommon() local
414 match(Cond1, m_ICmp(Pred1, m_Specific(LHS), m_ConstantInt(RHS1)))) { in widenCondCommon()
419 ConstantRange::makeExactICmpRegion(Pred1, RHS1->getValue()); in widenCondCommon()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3773 SDValue RHS1 = Op.getOperand(1); in isSaturatingConditional() local
3790 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1) in isSaturatingConditional()
3791 ? &RHS1 in isSaturatingConditional()
3797 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1; in isSaturatingConditional()
3817 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1) in isSaturatingConditional()
3822 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1) in isSaturatingConditional()
4045 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
4047 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
4053 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
8364 unsigned RHS1 = MI.getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2922 SDValue RHS1, RHS2; in OptimizeVFPBrcond() local
2924 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
2928 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
6199 unsigned RHS1 = MI->getOperand(3).getReg(); in EmitInstrWithCustomInserter() local
6203 .addReg(LHS1).addReg(RHS1)); in EmitInstrWithCustomInserter()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 8445 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); in Lower256IntVSETCC() local
8452 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), in Lower256IntVSETCC()
9799 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); in Lower256IntArith() local
9806 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), in Lower256IntArith()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 15123 SDValue RHS1 = extract128BitVector(RHS, 0, DAG, dl); in Lower256IntVSETCC() local
15130 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), in Lower256IntVSETCC()
19227 SDValue RHS1 = extract128BitVector(RHS, 0, DAG, dl); in Lower256IntArith() local
19234 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), in Lower256IntArith()
19256 SDValue RHS1 = extract256BitVector(RHS, 0, DAG, dl); in Lower512IntArith() local
19263 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), in Lower512IntArith()
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