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Searched refs:RLo (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMInstrInfo.td3941 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3943 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3945 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3947 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3950 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
3953 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]> {
3965 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
3967 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3969 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3973 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
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DARMInstrThumb2.td2586 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2588 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2592 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2594 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2598 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2600 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp19373 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMUL() local
19375 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT)); in LowerMUL()
19377 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMUL()
19553 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo); in LowerMULH() local
19555 RLo = DAG.getNode(ISD::SRL, dl, ExVT, RLo, DAG.getConstant(8, dl, ExVT)); in LowerMULH()
19557 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); in LowerMULH()
20285 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R); in LowerShift() local
20289 RLo = DAG.getBitcast(ExtVT, RLo); in LowerShift()
20293 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo, in LowerShift()
20297 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo); in LowerShift()
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