Searched refs:R_BIT (Results 1 – 9 of 9) sorted by relevance
1051 ((texGenEnabled & R_BIT) && planeR[0] != 0.0) || in r200_need_dis_texgen()1058 ((texGenEnabled & R_BIT) && planeR[1] != 0.0) || in r200_need_dis_texgen()1063 if (!(texGenEnabled & R_BIT)) { in r200_need_dis_texgen()1067 needtgenable |= R_BIT; in r200_need_dis_texgen()1073 ((texGenEnabled & R_BIT) && planeR[3] != 0.0)) { in r200_need_dis_texgen()1128 if (texUnit->TexGenEnabled & R_BIT) { in r200_validate_texgen()1174 if (needtgenable & (R_BIT)) { in r200_validate_texgen()1185 (texUnit->TexGenEnabled & R_BIT) ? texUnit->GenR.ObjectPlane : I + 8, in r200_validate_texgen()1202 if (needtgenable & (R_BIT)) { in r200_validate_texgen()1212 (texUnit->TexGenEnabled & R_BIT) ? texUnit->GenR.EyePlane : I + 8, in r200_validate_texgen()[all …]
431 if (texUnit->TexGenEnabled & R_BIT) { in texgen()523 else if (texUnit->TexGenEnabled & R_BIT) in validate_texgen_stage()534 if (texUnit->TexGenEnabled == (S_BIT|T_BIT|R_BIT)) { in validate_texgen_stage()
809 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) { in radeon_validate_texgen()825 if ( ((texUnit->TexGenEnabled & R_BIT) && in radeon_validate_texgen()844 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) { in radeon_validate_texgen()
269 if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) in radeonEmitArrays()
355 if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) in radeonEmitArrays()
493 if (texUnit->TexGenEnabled & R_BIT) { in update_texgen()
331 if (texUnit->TexGenEnabled & R_BIT) { in compute_texgen()
741 _mesa_set_enable(ctx, GL_TEXTURE_GEN_R, !!(genEnabled & R_BIT)); in pop_enable_group()802 _mesa_set_enable(ctx, GL_TEXTURE_GEN_R, !!(unit->TexGenEnabled & R_BIT)); in pop_texture_group()
1073 #define R_BIT 4 macro1075 #define STR_BITS (S_BIT | T_BIT | R_BIT)