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Searched refs:RefI (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DBitTracker.h142 BitRef RefI; member
146 BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {} in BitValue()
151 if (Type == Ref && !(RefI == V.RefI))
180 if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This) in meet()
192 RefI = V.RefI; // This may be irrelevant, but copy anyway. in meet()
197 RefI = Self; in meet()
223 if (V.RefI.Reg != 0) in ref()
224 return BitValue(V.RefI.Reg, V.RefI.Pos); in ref()
DBitTracker.cpp100 OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; in operator <<()
124 if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) { in operator <<()
126 SeqRef = (V.RefI.Pos == SV.RefI.Pos+1); in operator <<()
127 ConstRef = (V.RefI.Pos == SV.RefI.Pos); in operator <<()
129 if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start)) in operator <<()
131 if (ConstRef && V.RefI.Pos == SV.RefI.Pos) in operator <<()
144 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' in operator <<()
145 << SV.RefI.Pos+(Count-1) << ']'; in operator <<()
161 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-' in operator <<()
162 << SV.RefI.Pos+(Count-1) << ']'; in operator <<()
[all …]
DHexagonBitSimplify.cpp273 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) in isEqual()
276 if (RC2[B2+i].Type == BitTracker::BitValue::Ref && RC2[B2+i].RefI.Reg == 0) in isEqual()
1716 unsigned Reg = RC[I].RefI.Reg; in matchHalf()
1717 unsigned P = RC[I].RefI.Pos; // The RefI.Pos will be advanced by I-B. in matchHalf()
1736 if (RV.RefI.Reg != Reg) in matchHalf()
1738 if (RV.RefI.Pos != i+Pos) in matchHalf()
2084 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != RS.Reg) { in simplifyTstbit()
2085 const TargetRegisterClass *TC = MRI.getRegClass(V.RefI.Reg); in simplifyTstbit()
2090 BitTracker::RegisterRef RR(V.RefI.Reg, 0); in simplifyTstbit()
2092 P = V.RefI.Pos; in simplifyTstbit()
[all …]
DHexagonGenInsert.cpp236 unsigned Ind1 = BaseOrd[V1.RefI.Reg], Ind2 = BaseOrd[V2.RefI.Reg]; in operator ()()
240 assert(V1.RefI.Pos != V2.RefI.Pos && "Bit values should be different"); in operator ()()
241 return V1.RefI.Pos < V2.RefI.Pos; in operator ()()
664 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == VR) in findSelfReference()
675 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != VR) in findNonSelfReference()