Searched refs:RegArgs (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXMachineFunctionInfo.h | 35 DenseSet<unsigned> RegArgs; variable
73 reg_iterator argreg_begin() const { return RegArgs.begin(); } in argreg_begin()
74 reg_iterator argreg_end() const { return RegArgs.end(); } in argreg_end()
94 RegArgs.insert(Reg); in addArgReg()
97 name += utostr(RegArgs.size() - 1); in addArgReg()
107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) { in addVirtualRegister()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 196 SmallVectorImpl<unsigned> &RegArgs,
1563 SmallVectorImpl<unsigned> &RegArgs, in ProcessCallArgs() argument
1638 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1652 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1653 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
1842 SmallVector<unsigned, 4> RegArgs; in ARMEmitLibcall() local
1844 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes)) in ARMEmitLibcall()
1863 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) in ARMEmitLibcall()
1864 MIB.addReg(RegArgs[i]); in ARMEmitLibcall()
1954 SmallVector<unsigned, 4> RegArgs; in SelectCall() local
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 195 SmallVectorImpl<unsigned> &RegArgs,
1874 SmallVectorImpl<unsigned> &RegArgs, in ProcessCallArgs() argument
1978 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1993 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1994 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2236 SmallVector<unsigned, 4> RegArgs; in ARMEmitLibcall() local
2239 RegArgs, CC, NumBytes, false)) in ARMEmitLibcall()
2261 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) in ARMEmitLibcall()
2262 MIB.addReg(RegArgs[i], RegState::Implicit); in ARMEmitLibcall()
2370 SmallVector<unsigned, 4> RegArgs; in SelectCall() local
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 184 SmallVectorImpl<unsigned> &RegArgs,
1281 SmallVectorImpl<unsigned> &RegArgs, in processCallArgs() argument
1385 RegArgs.push_back(ArgReg); in processCallArgs()
1546 SmallVector<unsigned, 8> RegArgs; in fastLowerCall() local
1550 RegArgs, CC, NumBytes, IsVarArg)) in fastLowerCall()
1577 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) in fastLowerCall()
1578 MIB.addReg(RegArgs[II], RegState::Implicit); in fastLowerCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 1668 SmallVector<unsigned, 4> RegArgs; in DoSelectCall() local
1725 RegArgs.push_back(VA.getLocReg()); in DoSelectCall()
1831 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) in DoSelectCall()
1832 MIB.addReg(RegArgs[i]); in DoSelectCall()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3355 CfgVector<Variable *> RegArgs; in lowerCall() local
3383 RegArgs.emplace_back( in lowerCall()
3537 RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second)); in lowerCall()
3540 RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second)); in lowerCall()
3547 for (auto *RegArg : RegArgs) { in lowerCall()
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| D | IceTargetLoweringARM32.cpp | 3810 CfgVector<Variable *> RegArgs; in lowerCall() local
3812 RegArgs.emplace_back(legalizeToReg(FPArg.first, FPArg.second)); in lowerCall()
3815 RegArgs.emplace_back(legalizeToReg(GPRArg.first, GPRArg.second)); in lowerCall()
3822 for (auto *RegArg : RegArgs) { in lowerCall()
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