Searched refs:RegPos (Results 1 – 3 of 3) sorted by relevance
/external/llvm/lib/CodeGen/ |
D | LiveIntervalUnion.cpp | 35 LiveRange::const_iterator RegPos = Range.begin(); in unify() local 37 SegmentIter SegPos = Segments.find(RegPos->start); in unify() 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 41 if (++RegPos == RegEnd) in unify() 43 SegPos.advanceTo(RegPos->start); in unify() 51 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify() 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 62 LiveRange::const_iterator RegPos = Range.begin(); in extract() local 64 SegmentIter SegPos = Segments.find(RegPos->start); in extract() 73 RegPos = Range.advanceTo(RegPos, SegPos.start()); in extract() [all …]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | LiveIntervalUnion.cpp | 34 LiveInterval::iterator RegPos = VirtReg.begin(); in unify() local 36 SegmentIter SegPos = Segments.find(RegPos->start); in unify() 39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 40 if (++RegPos == RegEnd) in unify() 42 SegPos.advanceTo(RegPos->start); in unify() 50 for (; RegPos != RegEnd; ++RegPos, ++SegPos) in unify() 51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 61 LiveInterval::iterator RegPos = VirtReg.begin(); in extract() local 63 SegmentIter SegPos = Segments.find(RegPos->start); in extract() 72 RegPos = VirtReg.advanceTo(RegPos, SegPos.start()); in extract() [all …]
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/external/llvm/lib/Target/AMDGPU/ |
D | SIMachineScheduler.cpp | 1320 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local 1322 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler() 1334 std::map<unsigned, unsigned>::iterator RegPos = in SIScheduleBlockScheduler() local 1336 if (RegPos != LiveOutRegsNumUsages[PredID].end()) { in SIScheduleBlockScheduler() 1372 std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg); in SIScheduleBlockScheduler() local 1374 if (RegPos != PredOutRegs.end()) { in SIScheduleBlockScheduler()
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