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Searched refs:Registers (Results 1 – 25 of 146) sorted by relevance

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/external/v8/src/mips/
Dconstants-mips.cc19 const char* Registers::names_[kNumSimuRegisters] = {
38 const Registers::RegisterAlias Registers::aliases_[] = {
47 const char* Registers::Name(int reg) { in Name()
58 int Registers::Number(const char* name) { in Number()
/external/v8/src/mips64/
Dconstants-mips64.cc19 const char* Registers::names_[kNumSimuRegisters] = {
38 const Registers::RegisterAlias Registers::aliases_[] = {
47 const char* Registers::Name(int reg) { in Name()
58 int Registers::Number(const char* name) { in Number()
/external/v8/src/arm/
Dconstants-arm.cc36 const char* Registers::names_[kNumRegisters] = {
43 const Registers::RegisterAlias Registers::aliases_[] = {
94 int Registers::Number(const char* name) { in Number()
/external/libhevc/common/arm/
Dihevc_mem_fns.s67 @**************Variables Vs Registers*************************
99 @**************Variables Vs Registers*************************
138 @**************Variables Vs Registers*************************
170 @**************Variables Vs Registers*************************
208 @**************Variables Vs Registers*************************
242 @**************Variables Vs Registers*************************
/external/libavc/common/arm/
Dih264_mem_fns_neon.s72 @**************Variables Vs Registers*************************
101 @**************Variables Vs Registers*************************
139 @**************Variables Vs Registers*************************
169 @**************Variables Vs Registers*************************
206 @**************Variables Vs Registers*************************
238 @**************Variables Vs Registers*************************
Dih264_intra_pred_luma_4x4_a9q.s94 @**************Variables Vs Registers*****************************************
167 @**************Variables Vs Registers*****************************************
249 @**************Variables Vs Registers*****************************************
388 @**************Variables Vs Registers*****************************************
470 @**************Variables Vs Registers*****************************************
550 @**************Variables Vs Registers*****************************************
632 @**************Variables Vs Registers*****************************************
714 @**************Variables Vs Registers*****************************************
795 @**************Variables Vs Registers*****************************************
Dih264_intra_pred_luma_8x8_a9q.s96 @**************Variables Vs Registers*****************************************
184 @**************Variables Vs Registers*****************************************
257 @**************Variables Vs Registers*****************************************
337 @**************Variables Vs Registers*****************************************
448 @**************Variables Vs Registers*****************************************
541 @**************Variables Vs Registers*****************************************
632 @**************Variables Vs Registers*****************************************
752 @**************Variables Vs Registers*****************************************
870 @**************Variables Vs Registers*****************************************
971 @**************Variables Vs Registers*****************************************
/external/llvm/test/CodeGen/X86/
Dipra-inline-asm.ll7 ; CHECK-NOT: bar Clobbered Registers:{{.+}}
8 ; CHECK: bar Clobbered Registers:
14 ; CHECK: foo Clobbered Registers: AH AL AX CH CL CX DI DIL EAX ECX EDI RAX RCX RDI
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td31 // Mips CPU Registers
36 // Mips 64-bit CPU Registers
43 // Mips 32-bit FPU Registers
48 // Mips 64-bit (aliased) FPU Registers
61 // Mips Hardware Registers
67 // Registers
73 // General Purpose Registers
107 // General Purpose 64-bit Registers
141 /// Mips Single point precision FPU Registers
175 /// Mips Double point precision FPU Registers (aliased
[all …]
/external/mesa3d/src/mesa/swrast/
Ds_atifragshader.c37 GLfloat Registers[6][4]; /** six temporary registers */ member
237 COPY_4V(machine->PrevPassRegisters[i], machine->Registers[i]); in finish_pass()
251 COPY_4V(machine->Registers[idx], in handle_pass_op()
256 COPY_4V(machine->Registers[idx], machine->PrevPassRegisters[pass_tex]); in handle_pass_op()
258 apply_swizzle(machine->Registers[idx], swizzle); in handle_pass_op()
282 fetch_texel(ctx, tex_coords, 0.0F, idx, machine->Registers[idx]); in handle_sample_op()
339 machine->Registers[index - GL_REG_0_ATI]); in execute_shader()
526 dstp = machine->Registers[dstreg - GL_REG_0_ATI]; in execute_shader()
555 machine->Registers[i][j] = 0.0; in init_machine()
585 const GLfloat *colOut = machine.Registers[0]; in _swrast_exec_fragment_shader()
/external/v8/src/ppc/
Dconstants-ppc.cc15 const char* Registers::names_[kNumRegisters] = {
39 int Registers::Number(const char* name) { in Number()
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td41 // Mips CPU Registers
44 // Mips 64-bit CPU Registers
50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
66 // Mips 128-bit (aliased) MSA Registers
72 // Accumulator Registers
79 // Mips Hardware Registers
83 // Registers
87 // General Purpose Registers
121 // General Purpose 64-bit Registers
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.td46 // 32-bit Temporary Registers
53 // 128-bit Temporary Registers
88 // 32-bit Temporary Registers
91 // 128-bit Temporary Registers
103 // 32-bit Temporary Registers
106 // 128-bit Temporary Registers
122 // Special Registers
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td22 // Registers
25 // Special Registers used as stack pointer
29 // Special Registers used as the stack
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.cpp525 Registers.reserve(Regs.size()); in CodeGenRegBank()
541 for (unsigned i = 0, e = Registers.size(); i != e; ++i) in CodeGenRegBank()
542 Registers[i]->getSubRegs(*this); in CodeGenRegBank()
568 Reg = new CodeGenRegister(Def, Registers.size() + 1); in getReg()
569 Registers.push_back(Reg); in getReg()
614 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { in computeComposites()
615 CodeGenRegister *Reg1 = Registers[i]; in computeComposites()
700 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { in computeOverlaps()
701 CodeGenRegister *Reg = Registers[i]; in computeOverlaps()
726 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { in computeOverlaps()
[all …]
DRegisterInfoEmitter.cpp32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); in runEnums() local
34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); in runEnums()
50 for (unsigned i = 0, e = Registers.size(); i != e; ++i) in runEnums()
51 OS << " " << Registers[i]->getName() << " = " << in runEnums()
52 Registers[i]->EnumValue << ",\n"; in runEnums()
53 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && in runEnums()
55 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
/external/llvm/test/CodeGen/AArch64/
Dpreserve_mostcc.ll6 ; Registers r9-r15 should be saved before the call of a function
26 ; Registers r9-r15 don't need to be saved if one
/external/smali/
DREADME.md17 - [Registers wiki page](https://github.com/JesusFreke/smali/wiki/Registers)
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp958 for (auto &Reg : Registers) in CodeGenRegBank()
962 for (auto &Reg : Registers) in CodeGenRegBank()
972 for (auto &Reg : Registers) in CodeGenRegBank()
976 for (auto &Reg : Registers) in CodeGenRegBank()
982 for (auto &Reg : Registers) in CodeGenRegBank()
1031 Registers.emplace_back(Def, Registers.size() + 1); in getReg()
1032 Reg = &Registers.back(); in getReg()
1121 for (const auto &Reg1 : Registers) { in computeComposites()
1325 const auto &Registers = RegBank.getRegisters(); in computeUberSets() local
1328 assert(Registers.size() == Registers.back().EnumValue && in computeUberSets()
[all …]
DAsmWriterEmitter.cpp494 const std::deque<CodeGenRegister> &Registers) { in emitRegisterNameString() argument
496 SmallVector<std::string, 4> AsmNames(Registers.size()); in emitRegisterNameString()
498 for (const auto &Reg : Registers) { in emitRegisterNameString()
538 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { in emitRegisterNameString()
550 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName() local
554 Registers.front().TheDef->getValueAsString("Namespace"); in EmitGetRegisterName()
565 O << " assert(RegNo && RegNo < " << (Registers.size()+1) in EmitGetRegisterName()
571 emitRegisterNameString(O, R->getName(), Registers); in EmitGetRegisterName()
573 emitRegisterNameString(O, "", Registers); in EmitGetRegisterName()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8632Traits.h545 SmallBitVector Registers(RegisterSet::Reg_NUM);
551 Registers[RegisterSet::val] = true; \
553 Registers[RegisterSet::val] = true; \
555 Registers[RegisterSet::val] = true; \
557 Registers[RegisterSet::val] = true; \
559 Registers[RegisterSet::val] = false; \
561 Registers[RegisterSet::val] = false; \
563 Registers[RegisterSet::val] = false; \
565 Registers[RegisterSet::val] = false;
571 return Registers;
DIceTargetLoweringX8664Traits.h586 SmallBitVector Registers(RegisterSet::Reg_NUM);
594 Registers[RegisterSet::val] = true; \
596 Registers[RegisterSet::val] = true; \
598 Registers[RegisterSet::val] = true; \
600 Registers[RegisterSet::val] = true; \
602 Registers[RegisterSet::val] = false; \
604 Registers[RegisterSet::val] = false; \
606 Registers[RegisterSet::val] = false; \
608 Registers[RegisterSet::val] = false; \
615 return Registers;
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegisterInfo.td1 //WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-
24 // Registers
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeRegisterInfo.td37 // Registers
41 // General Purpose Registers
75 // Special Purpose Registers
/external/v8/src/s390/
Dconstants-s390.cc275 const char* Registers::names_[kNumRegisters] = {
294 int Registers::Number(const char* name) { in Number()

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