| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, in SelectBinaryOp() local
354 if (ResultReg == 0) return false; in SelectBinaryOp()
357 UpdateValueMap(I, ResultReg); in SelectBinaryOp()
380 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in SelectBinaryOp() local
382 if (ResultReg == 0) return false; in SelectBinaryOp()
385 UpdateValueMap(I, ResultReg); in SelectBinaryOp()
391 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in SelectBinaryOp() local
393 if (ResultReg != 0) { in SelectBinaryOp()
395 UpdateValueMap(I, ResultReg); in SelectBinaryOp()
408 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in SelectBinaryOp() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
325 ResultReg) in fastMaterializeAlloca()
329 return ResultReg; in fastMaterializeAlloca()
346 unsigned ResultReg = createResultReg(RC); in materializeInt() local
348 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
349 return ResultReg; in materializeInt()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
385 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
388 return ResultReg; in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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| D | AArch64InstrInfo.cpp | 3289 unsigned ResultReg = Root.getOperand(0).getReg(); in genFusedMultiply() local
3297 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) in genFusedMultiply()
3298 MRI.constrainRegClass(ResultReg, RC); in genFusedMultiply()
3308 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
3313 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
3319 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg) in genFusedMultiply()
3353 unsigned ResultReg = Root.getOperand(0).getReg(); in genMaddR() local
3359 if (TargetRegisterInfo::isVirtualRegister(ResultReg)) in genMaddR()
3360 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
3369 ResultReg) in genMaddR()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 414 unsigned ResultReg = in selectBinaryOp() local
417 if (!ResultReg) in selectBinaryOp()
421 updateValueMap(I, ResultReg); in selectBinaryOp()
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp() local
450 if (!ResultReg) in selectBinaryOp()
454 updateValueMap(I, ResultReg); in selectBinaryOp()
460 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
462 if (ResultReg) { in selectBinaryOp()
464 updateValueMap(I, ResultReg); in selectBinaryOp()
475 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 133 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
279 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
280 if (!ResultReg) in emitLogicalOp()
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
284 return ResultReg; in emitLogicalOp()
298 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
300 ResultReg) in fastMaterializeAlloca()
303 return ResultReg; in fastMaterializeAlloca()
319 unsigned ResultReg = createResultReg(RC); in materialize32BitInt() local
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 176 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
190 unsigned &ResultReg);
280 unsigned ResultReg = createResultReg(RC); in FastEmitInst_() local
283 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); in FastEmitInst_()
284 return ResultReg; in FastEmitInst_()
290 unsigned ResultReg = createResultReg(RC); in FastEmitInst_r() local
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) in FastEmitInst_r()
300 TII.get(TargetOpcode::COPY), ResultReg) in FastEmitInst_r()
303 return ResultReg; in FastEmitInst_r()
310 unsigned ResultReg = createResultReg(RC); in FastEmitInst_rr() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 89 unsigned &ResultReg, unsigned Alignment = 1);
98 unsigned &ResultReg);
349 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
488 ResultReg = createResultReg(RC); in X86FastEmitLoad()
490 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
697 unsigned &ResultReg) { in X86FastEmitExtend() argument
703 ResultReg = RR; in X86FastEmitExtend()
1319 unsigned ResultReg = 0; in X86SelectLoad() local
1320 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1324 updateValueMap(I, ResultReg); in X86SelectLoad()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
281 unsigned ResultReg = createResultReg(RC); in fastEmitInst_r() local
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
294 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
297 return ResultReg; in fastEmitInst_r()
304 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
322 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
325 return ResultReg; in fastEmitInst_rr()
332 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 87 unsigned &ResultReg);
177 unsigned &ResultReg) { in X86FastEmitLoad() argument
224 ResultReg = createResultReg(RC); in X86FastEmitLoad()
226 DL, TII.get(Opc), ResultReg), AM); in X86FastEmitLoad()
312 unsigned &ResultReg) { in X86FastEmitExtend() argument
317 ResultReg = RR; in X86FastEmitExtend()
811 unsigned ResultReg = 0; in X86SelectLoad() local
812 if (X86FastEmitLoad(VT, AM, ResultReg)) { in X86SelectLoad()
813 UpdateValueMap(I, ResultReg); in X86SelectLoad()
896 unsigned ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 516 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
518 TII.get(WebAssembly::COPY), ResultReg) in copyValue()
520 return ResultReg; in copyValue()
528 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
536 return ResultReg; in fastMaterializeAlloca()
544 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? in fastMaterializeConstant() local
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
552 return ResultReg; in fastMaterializeConstant()
606 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
445 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
446 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
462 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad() argument
476 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
524 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg); in PPCEmitLoad()
525 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg); in PPCEmitLoad()
534 if (ResultReg == 0) in PPCEmitLoad()
535 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2682 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
2688 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
2692 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
2693 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
2833 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
2846 BuildMI(MBB, MII, DL, InstDesc, ResultReg) in splitScalar64BitBCNT()
2850 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
2854 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in splitScalar64BitBCNT()
2878 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); in splitScalar64BitBFE() local
2889 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
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| /external/llvm/include/llvm/CodeGen/ |
| D | FastISel.h | 80 unsigned ResultReg; member
96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {} in CallLoweringInfo()
|