| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 77 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
88 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
89 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
90 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
91 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
92 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
93 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
94 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
95 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
96 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86ISelLowering.cpp | 424 setOperationAction(ISD::SETCC , MVT::i8 , Custom); in X86TargetLowering()
425 setOperationAction(ISD::SETCC , MVT::i16 , Custom); in X86TargetLowering()
426 setOperationAction(ISD::SETCC , MVT::i32 , Custom); in X86TargetLowering()
427 setOperationAction(ISD::SETCC , MVT::f32 , Custom); in X86TargetLowering()
428 setOperationAction(ISD::SETCC , MVT::f64 , Custom); in X86TargetLowering()
429 setOperationAction(ISD::SETCC , MVT::f80 , Custom); in X86TargetLowering()
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom); in X86TargetLowering()
725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
803 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); in X86TargetLowering()
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 83 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
96 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
97 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set
98 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than
99 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal
100 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to
101 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
102 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal
103 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than
104 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set
[all …]
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| D | X86TargetTransformInfo.cpp | 887 { ISD::SETCC, MVT::v2i64, 8 }, in getCmpSelInstrCost()
888 { ISD::SETCC, MVT::v4i32, 1 }, in getCmpSelInstrCost()
889 { ISD::SETCC, MVT::v8i16, 1 }, in getCmpSelInstrCost()
890 { ISD::SETCC, MVT::v16i8, 1 }, in getCmpSelInstrCost()
894 { ISD::SETCC, MVT::v2f64, 1 }, in getCmpSelInstrCost()
895 { ISD::SETCC, MVT::v4f32, 1 }, in getCmpSelInstrCost()
896 { ISD::SETCC, MVT::v2i64, 1 }, in getCmpSelInstrCost()
900 { ISD::SETCC, MVT::v4f64, 1 }, in getCmpSelInstrCost()
901 { ISD::SETCC, MVT::v8f32, 1 }, in getCmpSelInstrCost()
903 { ISD::SETCC, MVT::v4i64, 4 }, in getCmpSelInstrCost()
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | aarch64-neon-v1i1-setcc.ll | 4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
8 ; operands of SETCC have been legalized.
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 4 ** DONE Problem with asymmetric SETCC operations
96 ** Create test case for each Illegal SETCC case
97 The DAG combiner may someimes produce illegal i16 SETCC instructions.
99 *** TODO SETCC (ctlz x), 5) == const
100 *** TODO SETCC (and load, const) == const
101 *** DONE SETCC (zext x) == const
102 *** TODO SETCC (sext x) == const
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| D | BlackfinInstrInfo.td | 562 multiclass SETCC<PatFrag opnode, PatFrag invnode, string cond, string suf=";"> {
580 defm SETEQ : SETCC<seteq, setne, "==">;
581 defm SETLT : SETCC<setlt, setge, "<">;
582 defm SETLE : SETCC<setle, setgt, "<=">;
583 defm SETULT : SETCC<setult, setuge, "<", " (iu);">;
584 defm SETULE : SETCC<setule, setugt, "<=", " (iu);">;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 165 case ISD::SETCC: in LegalizeOp()
223 else if (Node->getOpcode() == ISD::SETCC) in LegalizeOp()
361 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), in UnrollVSETCC()
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| D | LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); in ScalarizeVecRes_SETCC()
284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_VSETCC()
435 case ISD::SETCC: in SplitVectorResult()
971 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
1182 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
1183 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
1244 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
1952 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, in WidenVecRes_SETCC()
2007 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), in WidenVecRes_VSETCC()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 94 setOperationAction(ISD::SETCC, MVT::i1, Custom); in PTXTargetLowering()
113 case ISD::SETCC: in LowerOperation()
166 return DAG.getNode(ISD::SETCC, dl, MVT::i1, Op0, Op1, Op2); in LowerSETCC()
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| D | promote-setcc.ll | 3 ; The DAG combiner may sometimes create illegal i16 SETCC operations when run
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 344 SETCC, enumerator
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | setcc-01.ll | 1 ; Test SETCC for every integer condition. The tests here assume that
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| D | setcc-02.ll | 1 ; Test SETCC for every floating-point condition. The tests here assume that
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.h | 42 SETCC, enumerator
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| D | LanaiISelLowering.cpp | 73 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
178 case ISD::SETCC: in LowerOperation()
968 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); in LowerSETCCE()
982 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); in LowerSETCC()
1107 case LanaiISD::SETCC: in getTargetNodeName()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 117 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SystemZTargetLowering()
118 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SystemZTargetLowering()
119 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SystemZTargetLowering()
120 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SystemZTargetLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 372 SETCC, enumerator
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
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| D | MSP430ISelLowering.cpp | 108 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
109 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
188 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
1127 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; in getTargetNodeName()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 52 SETCC, enumerator
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | pr24636.ll | 12 ; We used to crash because a bad DAGCombine was creating i32-typed SETCC nodes,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
301 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
363 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); in ScalarizeVecRes_SETCC()
404 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_VSETCC()
614 case ISD::SETCC: in SplitVectorResult()
1459 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; in SplitVectorOperand()
2003 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); in SplitVecOp_VSETCC()
2004 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); in SplitVecOp_VSETCC()
2071 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; in WidenVectorResult()
2988 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT, in WidenVecRes_SETCC()
[all …]
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| D | LegalizeVectorOps.cpp | 294 case ISD::SETCC: in LegalizeOp()
697 case ISD::SETCC: in Expand()
1057 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
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| D | DAGCombiner.cpp | 736 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1393 case ISD::SETCC: return visitSETCC(N); in visit()
2922 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) { in visitANDLike()
3657 TLI.isOperationLegal(ISD::SETCC, LL.getValueType())))) { in visitORLike()
4180 case ISD::SETCC: in visitXOR()
4423 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
5220 if (N0.getOpcode() == ISD::SETCC) { in visitSELECT()
5340 if (Mask.getOpcode() != ISD::SETCC) in visitMSCATTER()
5401 if (Mask.getOpcode() == ISD::SETCC) { in visitMSTORE()
5475 if (Mask.getOpcode() != ISD::SETCC) in visitMGATHER()
[all …]
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