| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 727 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
752 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 865 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 167 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break; in getFCmpCondCode()
189 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 177 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode()
189 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
204 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 315 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: in Select()
336 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 79 SETULE unimplemented
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 54 IntRegs:$fval, SETULE)),
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 49 defm LE_U : ComparisonInt<SETULE, "le_u">;
|
| D | WebAssemblyISelLowering.cpp | 78 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 233 case ISD::SETULE: in softenSetCCOperands()
1581 case ISD::SETULE: in SimplifySetCC()
1603 case ISD::SETULE: { in SimplifySetCC()
1763 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
1784 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC()
1877 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
1878 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
1889 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1950 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
2156 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
|
| D | SelectionDAGDumper.cpp | 344 case ISD::SETULE: return "setule"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 972 case ISD::SETULE: in PromoteSetCCOperands()
2838 case ISD::SETULE: LowCC = ISD::SETULE; break; in IntegerExpandSetCCOperands()
2873 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
2905 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 550 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
563 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
576 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
589 defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">;
598 defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrQPX.td | 1016 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETULE),
1063 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETULE),
1123 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETULE)),
1144 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETULE)),
1165 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETULE)),
|
| D | PPCISelDAGToDAG.cpp | 2103 case ISD::SETULE: in getPredicateForSetCC()
2133 case ISD::SETULE: in getCRIdxForSetCC()
2164 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2172 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
2208 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
2217 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
|
| D | PPCInstrInfo.td | 2971 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3185 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3213 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3253 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3281 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3308 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3339 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3367 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
3396 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
3417 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)),
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2086 case ISD::SETULE: in SimplifySetCC()
2108 case ISD::SETULE: { in SimplifySetCC()
2247 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
2261 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) in SimplifySetCC()
2369 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); in SimplifySetCC()
2560 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
|
| D | LegalizeIntegerTypes.cpp | 819 case ISD::SETULE: in PromoteSetCCOperands()
2515 case ISD::SETULE: LowCC = ISD::SETULE; break; in IntegerExpandSetCCOperands()
2545 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || in IntegerExpandSetCCOperands()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 781 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULE),
818 (i32 GPR:$T), (i32 GPR:$F), SETULE),
848 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULE), bb:$T),
|
| D | MBlazeInstrFPU.td | 200 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULE),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 558 case ISD::SETULE: in getPredicateForSetCC()
592 case ISD::SETULE: in getCRIdxForSetCC()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 427 case ISD::SETULE: in NegateCC()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 964 case ISD::SETULE: in isLegalDSPCondCode()
1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) in performVSELECTCombine()
1715 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1721 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1825 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 655 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
679 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1024 case ISD::SETULE: return ARMCC::LS; in IntCCToARMCC()
1051 case ISD::SETULE: CondCode = ARMCC::LE; break; in FPCCToARMCC()
2667 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
2678 case ISD::SETULE: in getARMCmp()
2681 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3459 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; in LowerVSETCC()
3493 case ISD::SETULE: Swap = true; in LowerVSETCC()
7816 case ISD::SETULE: in PerformSELECT_CCCombine()
7820 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); in PerformSELECT_CCCombine()
7826 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && in PerformSELECT_CCCombine()
|