Home
last modified time | relevance | path

Searched refs:SEXT (Results 1 – 13 of 13) sorted by relevance

/external/llvm/test/Transforms/InstCombine/
Dsub.ll455 ; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[ICMP]] to <2 x i32>
456 ; CHECK-NEXT: ret <2 x i32> [[SEXT]]
465 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32
466 ; CHECK-NEXT: ret i32 [[SEXT]]
496 ; CHECK-NEXT: [[SEXT:%.*]] = sext i16 %a to i32
498 ; CHECK-NEXT: [[RET:%.*]] = sub nsw i32 [[SEXT]], [[SEXT1]]
Dcast.ll261 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %X, 24
262 ; CHECK-NEXT: ret i32 [[SEXT]]
581 ; CHECK-NEXT: [[SEXT:%.*]] = ashr exact i64 [[C]], 32
582 ; CHECK-NEXT: [[D:%.*]] = or i64 [[SEXT]], 1
595 ; CHECK-NEXT: [[SEXT:%.*]] = add i64 [[D]], -4294967296
596 ; CHECK-NEXT: [[E:%.*]] = ashr exact i64 [[SEXT]], 32
612 ; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[E]], 32
613 ; CHECK-NEXT: [[F:%.*]] = ashr exact i64 [[SEXT]], 32
1320 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[ICMP]] to i32
1321 ; CHECK-NEXT: ret i32 [[SEXT]]
Dor.ll450 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 %y to i32
451 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], %x
452 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SEXT]], [[OR]]
Dlogical-select.ll267 ; CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> %cmp to <4 x i32>
268 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
270 ; CHECK-NEXT: [[NEG:%.*]] = xor <4 x i32> [[SEXT]], <i32 -1, i32 -1, i32 -1, i32 -1>
Dshift.ll996 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33>
997 ; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], <i65 33, i65 33>
/external/llvm/lib/Target/AMDGPU/
DSIDefines.h94 SEXT = 1 << 0 // Integer sign-extend modifier enumerator
/external/llvm/test/CodeGen/X86/
Dcodegen-prepare-extload.ll62 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
350 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
351 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementpt…
Dcodegen-prepare-addrmode-sext.ll257 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
258 ; CHECK: getelementptr inbounds i8, i8* %base, i64 [[SEXT]]
279 ; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64
280 ; CHECK: getelementptr inbounds i8, i8* %base, i64 [[SEXT]]
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp443 if (InputModifiers & SISrcMods::SEXT) in printOperandAndIntInputMods()
446 if (InputModifiers & SISrcMods::SEXT) in printOperandAndIntInputMods()
/external/llvm/test/CodeGen/AArch64/
Darm64-register-offset-addressing.ll14 ; These tests are trying to form SEXT and ZEXT operations that never leave i64
Darm64-codegen-prepare-extload.ll56 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32
57 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
343 ; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32
344 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementpt…
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td1775 def SEXT : ExtensionPseudo<
1949 (SEXT (i8 (EXTRACT_SUBREG i16:$src, sub_lo)))>;
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp83 Operand |= Sext ? SISrcMods::SEXT : 0; in getIntModifiersOperand()