| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
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| D | SIISelLowering.cpp | 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); in SITargetLowering()
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| D | AMDGPUISelLowering.cpp | 706 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
735 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1323 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1324 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
2109 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
2674 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
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| D | AMDGPUISelDAGToDAG.cpp | 466 case ISD::SIGN_EXTEND_INREG: in Select()
1310 case ISD::SIGN_EXTEND_INREG: { in SelectS_BFE()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 380 SIGN_EXTEND_INREG, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 413 SIGN_EXTEND_INREG, enumerator
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 71 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
462 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
535 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), in PromoteIntRes_SIGN_EXTEND_INREG()
667 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1016 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1110 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
2154 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
2168 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
2181 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
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| D | LegalizeVectorOps.cpp | 189 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
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| D | DAGCombiner.cpp | 724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) in SExtPromoteOperand()
736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, in SExtPromoteOperand()
1082 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); in visit()
3399 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) in visitSRA()
3400 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, in visitSRA()
4004 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, in visitSIGN_EXTEND()
4010 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, in visitSIGN_EXTEND()
4617 if (Opc == ISD::SIGN_EXTEND_INREG) { in ReduceLoadWidth()
4744 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); in visitSIGN_EXTEND_INREG()
4751 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && in visitSIGN_EXTEND_INREG()
[all …]
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| D | SelectionDAG.cpp | 1817 case ISD::SIGN_EXTEND_INREG: { in ComputeMaskedBits()
2122 case ISD::SIGN_EXTEND_INREG: in ComputeNumSignBits()
2827 case ISD::SIGN_EXTEND_INREG: { in getNode()
3017 case ISD::SIGN_EXTEND_INREG: in getNode()
4497 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && in getNode()
6034 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; in getOperationName()
6462 case ISD::SIGN_EXTEND_INREG: in UnrollVectorOp()
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| D | LegalizeTypes.h | 201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, in SExtPromotedInteger()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 84 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
556 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
640 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
796 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1329 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
2448 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
2462 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
2475 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
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| D | LegalizeVectorOps.cpp | 327 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
679 case ISD::SIGN_EXTEND_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 244 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; in getOperationName()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 69 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PTXTargetLowering()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
874 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BlackfinTargetLowering()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal); in NVPTXTargetLowering()
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in NVPTXTargetLowering()
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); in NVPTXTargetLowering()
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); in NVPTXTargetLowering()
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in NVPTXTargetLowering()
4116 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in IsMulWideOperandDemotable()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MSP430TargetLowering()
987 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, in LowerSIGN_EXTEND()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 108 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 369 N.getOpcode() == ISD::SIGN_EXTEND_INREG) { in getExtendTypeForNode()
371 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG) in getExtendTypeForNode()
1512 assert(N->getOpcode() == ISD::SIGN_EXTEND_INREG); in isBitfieldExtractOpFromSExtInReg()
1697 case ISD::SIGN_EXTEND_INREG: in isBitfieldExtractOp()
2605 case ISD::SIGN_EXTEND_INREG: in Select()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in MipsTargetLowering()
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in MipsTargetLowering()
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in MipsTargetLowering()
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