Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 435 SIGN_EXTEND_VECTOR_INREG, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 329 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
683 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
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| D | SelectionDAGDumper.cpp | 246 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 622 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
2130 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
2441 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2458 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
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| D | LegalizeIntegerTypes.cpp | 106 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3357 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
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| D | DAGCombiner.cpp | 1399 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N); in visit()
5787 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in tryToFoldExtendOfConstant()
5824 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
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| D | SelectionDAG.cpp | 1059 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); in getSignExtendVectorInReg()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 899 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4577 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
4778 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 852 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
853 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
854 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
1057 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom); in X86TargetLowering()
1058 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom); in X86TargetLowering()
1059 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom); in X86TargetLowering()
16486 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) && in LowerExtendedLoad()
21697 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
27571 : ISD::SIGN_EXTEND_VECTOR_INREG, in reduceVMULWidth()
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