| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 129 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
132 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
134 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
136 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
138 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
140 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
142 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
144 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
146 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
148 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
217 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
223 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
224 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
225 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost()
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
[all …]
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| D | AArch64ISelLowering.cpp | 173 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
174 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
175 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
470 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
551 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
560 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); in AArch64TargetLowering()
562 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); in AArch64TargetLowering()
565 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); in AArch64TargetLowering()
567 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); in AArch64TargetLowering()
570 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 575 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
576 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, in getCastInstrCost()
578 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
579 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
580 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, in getCastInstrCost()
581 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
582 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
673 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
674 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, in getCastInstrCost()
[all …]
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| D | X86IntrinsicsInfo.h | 501 ISD::SINT_TO_FP, 0),
503 ISD::SINT_TO_FP, 0), // no rm
505 ISD::SINT_TO_FP, 0),
507 ISD::SINT_TO_FP, 0),
509 ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er
571 ISD::SINT_TO_FP, 0),
573 ISD::SINT_TO_FP, 0),
575 ISD::SINT_TO_FP, ISD::SINT_TO_FP),
577 ISD::SINT_TO_FP, 0),
579 ISD::SINT_TO_FP, 0),
[all …]
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| D | README-FPStack.txt | 49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 195 case ISD::SINT_TO_FP: in LegalizeOp()
304 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) || in ExpandUINT_TO_FLOAT()
330 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
332 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
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| D | LegalizeFloatTypes.cpp | 96 case ISD::SINT_TO_FP: in SoftenFloatResult()
540 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
874 case ISD::SINT_TO_FP: in ExpandFloatResult()
1172 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1183 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeDAG.cpp | 805 case ISD::SINT_TO_FP: in LegalizeOp()
2548 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2557 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2600 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2664 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2665 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
3134 case ISD::SINT_TO_FP: in ExpandNode()
3136 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
3829 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
3875 case ISD::SINT_TO_FP: in PromoteNode()
[all …]
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| D | LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
467 case ISD::SINT_TO_FP: in SplitVectorResult()
987 case ISD::SINT_TO_FP: in SplitVectorOperand()
1288 case ISD::SINT_TO_FP: in WidenVectorResult()
2039 case ISD::SINT_TO_FP: in WidenVectorOperand()
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| D | FastISel.cpp | 196 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeRegForValue()
967 return SelectCast(I, ISD::SINT_TO_FP); in SelectOperator()
|
| /external/llvm/test/CodeGen/X86/ |
| D | pr23273.ll | 5 ; for SINT_TO_FP wrongly assumed that the target had at least SSE2.
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | dagcombiner-bug-illegal-vec4-int-to-fp.ll | 7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 340 case ISD::SINT_TO_FP: in LegalizeOp()
387 case ISD::SINT_TO_FP: in Promote()
983 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
1010 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
1012 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
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| D | LegalizeDAG.cpp | 964 case ISD::SINT_TO_FP: in LegalizeOp()
2364 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2373 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2419 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2489 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2490 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
2926 case ISD::SINT_TO_FP: in ExpandNode()
2928 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
3998 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
4056 case ISD::SINT_TO_FP: in PromoteNode()
[all …]
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| D | LegalizeFloatTypes.cpp | 109 case ISD::SINT_TO_FP: in SoftenFloatResult()
707 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
1044 case ISD::SINT_TO_FP: in ExpandFloatResult()
1411 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1423 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
1908 case ISD::SINT_TO_FP: in PromoteFloatResult()
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| D | SelectionDAGDumper.cpp | 254 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 372 SINT_TO_FP, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | README-FPStack.txt | 49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 405 SINT_TO_FP, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SPUTargetLowering()
343 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in SPUTargetLowering()
344 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in SPUTargetLowering()
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SPUTargetLowering()
384 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SPUTargetLowering()
2496 (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
2823 case ISD::SINT_TO_FP: in LowerOperation()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 116 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
117 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
123 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
263 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
372 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
379 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
390 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
396 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
517 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
644 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); in addTypeForNEON()
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3047 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
3049 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
3072 case ISD::SINT_TO_FP: in LowerINT_TO_FP()
4702 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
4703 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
4732 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
4733 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerSDIV_v4i16()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 84 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AlphaTargetLowering()
619 case ISD::SINT_TO_FP: { in LowerOperation()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 329 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
377 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
719 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1254 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2000 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
|