| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 325 SMIN, SMAX, UMIN, UMAX, enumerator
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| D | SelectionDAG.h | 1168 case ISD::SMIN:
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 972 X86_INTRINSIC_DATA(avx512_mask_pmins_b_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
973 X86_INTRINSIC_DATA(avx512_mask_pmins_b_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
974 X86_INTRINSIC_DATA(avx512_mask_pmins_b_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
975 X86_INTRINSIC_DATA(avx512_mask_pmins_d_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
976 X86_INTRINSIC_DATA(avx512_mask_pmins_d_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
977 X86_INTRINSIC_DATA(avx512_mask_pmins_d_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
978 X86_INTRINSIC_DATA(avx512_mask_pmins_q_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
979 X86_INTRINSIC_DATA(avx512_mask_pmins_q_256, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
980 X86_INTRINSIC_DATA(avx512_mask_pmins_q_512, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
981 X86_INTRINSIC_DATA(avx512_mask_pmins_w_128, INTR_TYPE_2OP_MASK, ISD::SMIN, 0),
[all …]
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| D | X86ISelLowering.cpp | 757 setOperationAction(ISD::SMIN, MVT::v8i16, Legal); in X86TargetLowering()
892 setOperationAction(ISD::SMIN, MVT::v16i8, Legal); in X86TargetLowering()
893 setOperationAction(ISD::SMIN, MVT::v4i32, Legal); in X86TargetLowering()
1052 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom); in X86TargetLowering()
1316 setOperationAction(ISD::SMIN, MVT::v16i32, Legal); in X86TargetLowering()
1317 setOperationAction(ISD::SMIN, MVT::v8i64, Legal); in X86TargetLowering()
1476 setOperationAction(ISD::SMIN, MVT::v64i8, Legal); in X86TargetLowering()
1477 setOperationAction(ISD::SMIN, MVT::v32i16, Legal); in X86TargetLowering()
1560 setOperationAction(ISD::SMIN, VT, Legal); in X86TargetLowering()
21759 case ISD::SMIN: in LowerOperation()
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| /external/llvm/test/Transforms/InstCombine/ |
| D | select.ll | 608 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
1273 ; SMIN(SMIN(X, 11), 92) -> SMIN(X, 11)
1321 ; SMIN(SMIN(X, 92), 11) -> SMIN(X, 11)
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| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | select.ll | 484 ; SMIN(SMIN(x, y), x) -> SMIN(x, y)
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 207 case ISD::SMIN: return "smin"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 331 case ISD::SMIN: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 114 case ISD::SMIN: in ScalarizeVectorResult()
692 case ISD::SMIN: in SplitVectorResult()
2095 case ISD::SMIN: in WidenVectorResult()
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| D | LegalizeIntegerTypes.cpp | 78 case ISD::SMIN: in PromoteIntegerResult()
1382 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
1684 case ISD::SMIN: in getExpandedMinMaxOps()
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| D | SelectionDAG.cpp | 2461 case ISD::SMIN: in computeKnownBits()
2606 case ISD::SMIN: in ComputeNumSignBits()
3243 case ISD::SMIN: return std::make_pair(C1.sle(C2) ? C1 : C2, true); in FoldValue()
3526 case ISD::SMIN: in getNode()
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| D | LegalizeDAG.cpp | 3129 case ISD::SMIN: in ExpandNode()
3138 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
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| D | SelectionDAGBuilder.cpp | 2780 case SPF_SMIN: Opc = ISD::SMIN; break; in visitSelect()
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| D | DAGCombiner.cpp | 1371 case ISD::SMIN: in visit()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 225 setTargetDAGCombine(ISD::SMIN); in SITargetLowering()
2701 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
2805 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
2871 case ISD::SMIN: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 334 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 873 setOperationAction(ISD::SMIN, VT, Expand); in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 699 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2297 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
9023 case ISD::SMIN: in tryMatchAcrossLaneShuffleForReduction()
9097 if (Op != ISD::SMAX && Op != ISD::UMAX && Op != ISD::SMIN && in performAcrossLaneMinMaxReductionCombine()
9131 (Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) || in performAcrossLaneMinMaxReductionCombine()
10124 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV); in ReplaceNodeResults()
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| D | AArch64InstrInfo.td | 2998 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 399 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp,
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3168 ### SMIN ### subsection
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 148 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2987 ? ISD::SMIN : ISD::SMAX; in LowerINTRINSIC_WO_CHAIN()
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