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Searched refs:SRC1 (Results 1 – 12 of 12) sorted by relevance

/external/bison/lib/
Dbitset.h218 #define bitset_and(DST, SRC1, SRC2) BITSET_AND_ (DST, SRC1, SRC2) argument
221 #define bitset_and_cmp(DST, SRC1, SRC2) BITSET_AND_CMP_ (DST, SRC1, SRC2) argument
224 #define bitset_andn(DST, SRC1, SRC2) BITSET_ANDN_ (DST, SRC1, SRC2) argument
227 #define bitset_andn_cmp(DST, SRC1, SRC2) BITSET_ANDN_CMP_ (DST, SRC1, SRC2) argument
230 #define bitset_or(DST, SRC1, SRC2) BITSET_OR_ (DST, SRC1, SRC2) argument
233 #define bitset_or_cmp(DST, SRC1, SRC2) BITSET_OR_CMP_ (DST, SRC1, SRC2) argument
236 #define bitset_xor(DST, SRC1, SRC2) BITSET_XOR_ (DST, SRC1, SRC2) argument
239 #define bitset_xor_cmp(DST, SRC1, SRC2) BITSET_XOR_CMP_ (DST, SRC1, SRC2) argument
244 #define bitset_and_or(DST, SRC1, SRC2, SRC3) \ argument
245 BITSET_AND_OR_ (DST, SRC1, SRC2, SRC3)
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Dbbitset.h164 #define BITSET_CHECK3_(DST, SRC1, SRC2) \ argument
165 if (!BITSET_COMPATIBLE_ (DST, SRC1) \
168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ argument
169 if (!BITSET_COMPATIBLE_ (DST, SRC1) || !BITSET_COMPATIBLE_ (DST, SRC2) \
230 #define BITSET_AND_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_ (DST, SRC1, SRC2) argument
231 #define BITSET_AND_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_cmp (DST, SRC1, SRC2) argument
234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2) argument
235 #define BITSET_ANDN_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn_cmp (DST, SRC1, SRC2) argument
238 #define BITSET_OR_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_ (DST, SRC1, SRC2) argument
239 #define BITSET_OR_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_cmp (DST, SRC1, SRC2) argument
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/external/llvm/test/CodeGen/Thumb/
Dcopy_thumb.ll9 ; CHECK-LOLOMOV: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
10 ; CHECK-LOLOMOV-NEXT: mov [[SRC1]], [[SRC2:r[01]]]
19 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
20 ; CHECK-NOLOLOMOV: push {[[SRC1:r[01]]]}
22 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
24 ; CHECK-NOLOLOMOV-NEXT: pop {[[SRC1]]}
25 ; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
/external/ltp/testcases/kernel/module/query_module/
DMakefile25 SRC1=dummy_query_mod.c dummy_query_mod_dep.c macro
26 OBJS=$(SRC1:.c=.o)
32 $(OBJS): $(SRC1)
33 $(CC) -DEXPORT_SYMTAB $(MODCFLAGS) -c $(SRC1) -Wall
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
211 FLD_S( SRC1 ) /* F5 F4 */
295 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
297 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
299 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
386 FLD_S( SRC1 ) /* F1 F4 */
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Dx86_xform2.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
197 FLD_S( SRC1 ) /* F1 F4 */
264 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
266 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
268 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
345 FLD_S( SRC1 ) /* F1 F4 */
[all …]
Dx86_xform4.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
218 FLD_S( SRC1 ) /* F5 F4 */
305 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
307 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
309 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
404 FLD_S( SRC1 ) /* F5 F4 */
[all …]
Dx86_cliptest.S37 #define SRC1 REGOFF(4, ESI) macro
181 MOV_L( SRC1, EBX )
230 FLD_S( SRC1 ) /* F1 F0 F3 */
347 MOV_L( SRC1, EBX )
/external/llvm/test/CodeGen/X86/
Dmachine-cp.ll69 ; CHECK: psllw $7, [[SRC1:%xmm[0-9]+]]
70 ; CHECK-NEXT: pand {{.*}}(%rip), [[SRC1]]
71 ; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]]
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll58 ; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
61 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
117 ; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
122 ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
Dmul.ll112 ; SI: s_load_dword [[SRC1:s[0-9]+]],
113 ; SI: s_mul_i32 [[SRESULT:s[0-9]+]], [[SRC0]], [[SRC1]]
/external/webp/src/dsp/
Drescaler_neon.c31 #define STORE_32x8(SRC0, SRC1, DST) do { \ argument
33 vst1q_u32((DST) + 4, SRC1); \