Home
last modified time | relevance | path

Searched refs:SREG (Results 1 – 17 of 17) sorted by relevance

/external/libunwind/src/mips/
Dgetcontext-android.S36 # define SREG(X) \ macro
46 # define SREG(X) sd $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X) ($4) macro
56 SREG (0)
57 SREG (1)
58 SREG (2)
59 SREG (3)
60 SREG (4)
61 SREG (5)
62 SREG (6)
63 SREG (7)
[all …]
Dgetcontext.S37 # define SREG(X) \ macro
47 # define SREG(X) sd $X, (LINUX_UC_MCONTEXT_GREGS + 8 * X) ($4) macro
57 SREG (1)
58 SREG (0)
59 SREG (2)
60 SREG (3)
61 SREG (4)
62 SREG (5)
63 SREG (6)
64 SREG (7)
[all …]
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td297 // sub / add which can clobber SREG.
298 let Defs = [SP, SREG],
322 Defs = [SREG] in
332 (implicit SREG)]>;
344 (implicit SREG)]>;
348 let Uses = [SREG] in
355 (implicit SREG)]>;
364 let Uses = [SREG] in
369 (implicit SREG)]>;
378 (implicit SREG)]>,
[all …]
DAVRRegisterInfo.td211 def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>;
212 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>
DAVRInstrFormats.td553 let Defs = [SREG];
567 let Uses = [SREG];
575 let Defs = [SREG];
/external/llvm/test/CodeGen/AMDGPU/
Dtrunc-store-i1.ll7 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
26 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
Dsetuo.ll5 ; CHECK: v_cmp_u_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]
Dseto.ll5 ; CHECK: v_cmp_o_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], [[SREG:s[0-9]+]], [[SREG]]
Ddebugger-emit-prologue.ll5 ; CHECK: debug_private_segment_buffer_sgpr = [[SREG:[0-9]+]]
20 ; CHECK: DebuggerPrivateSegmentBufferSGPR: s[[SREG]]
Dtrunc.ll23 ; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
Dglobal_atomics_i64.ll862 ; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x11940
863 ; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{…
Dglobal_atomics.ll14 ; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x8ca0
15 ; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}}
/external/llvm/test/CodeGen/ARM/
Dfp16-args.ll35 ; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
36 ; HARD-NEXT: vmov [[REG0:r[0-9]+]], [[SREG]]
/external/llvm/test/CodeGen/AArch64/
Darm64-sitofp-combine-chains.ll14 ; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
Darm64-xaluo.ll196 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
197 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
366 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
367 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
556 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
557 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
Darm64-inline-asm.ll251 ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}}
252 ; CHECK: sqxtn h0, [[SREG]]
/external/vixl/src/aarch64/
Doperands-aarch64.cc170 #define SREG(n) s##n, macro
171 const VRegister VRegister::sregisters[] = {AARCH64_REGISTER_CODE_LIST(SREG)};
172 #undef SREG