| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 428 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
432 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
436 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
440 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
445 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
449 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
453 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
457 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| D | ARMISelLowering.cpp | 142 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
791 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
796 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
7180 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
7249 case ISD::SREM: in ReplaceNodeResults()
12010 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
12013 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
12028 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
12031 N->getOpcode() == ISD::SREM; in getDivRemArgList()
12103 bool isSigned = N->getOpcode() == ISD::SREM; in LowerREM()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 83 setOperationAction(ISD::SREM, MVT::i16, Expand); in BlackfinTargetLowering()
84 setOperationAction(ISD::SREM, MVT::i32, Expand); in BlackfinTargetLowering()
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| /external/llvm/test/CodeGen/ARM/ |
| D | divmod-eabi.ll | 3 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 97 setOperationAction(ISD::SREM , MVT::i64, Custom); in AlphaTargetLowering()
679 case ISD::SREM: in LowerOperation()
700 case ISD::SREM: opstr = "__remq"; break; in LowerOperation()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1675 case ISD::SREM: in selectDivRem()
1696 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1799 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
1800 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
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| D | MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
217 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
267 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2023 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 144 case ISD::SREM: in LegalizeOp()
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| D | SelectionDAGBuilder.h | 485 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| D | LegalizeVectorTypes.cpp | 108 case ISD::SREM: in ScalarizeVectorResult()
491 case ISD::SREM: in SplitVectorResult()
1264 case ISD::SREM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2010 case ISD::SREM: in ComputeMaskedBits()
2658 case ISD::SREM: in FoldConstantArithmetic()
2729 case ISD::SREM: in getNode()
3027 case ISD::SREM: in getNode()
3055 case ISD::SREM: in getNode()
5979 case ISD::SREM: return "srem"; in getOperationName()
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| D | FastISel.cpp | 904 return SelectBinaryOp(I, ISD::SREM); in SelectOperator()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 102 setOperationAction(ISD::SREM, MVT::i32, Expand); in SystemZTargetLowering()
104 setOperationAction(ISD::SREM, MVT::i64, Expand); in SystemZTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 180 setOperationAction(ISD::SREM, MVT::i8, Expand); in SPUTargetLowering()
186 setOperationAction(ISD::SREM, MVT::i16, Expand); in SPUTargetLowering()
192 setOperationAction(ISD::SREM, MVT::i32, Expand); in SPUTargetLowering()
198 setOperationAction(ISD::SREM, MVT::i64, Expand); in SPUTargetLowering()
204 setOperationAction(ISD::SREM, MVT::i128, Expand); in SPUTargetLowering()
423 setOperationAction(ISD::SREM, VT, Expand); in SPUTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 158 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
164 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 182 case ISD::SREM: return "srem"; in getOperationName()
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| D | SelectionDAGBuilder.h | 836 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| D | LegalizeVectorOps.cpp | 267 case ISD::SREM: in LegalizeOp()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 151 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
157 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 82 setOperationAction(ISD::SREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 970 case ISD::SREM: in canOpTrap()
1682 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 102 setOperationAction(ISD::SREM, MVT::i32, Expand); in MBlazeTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 139 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
143 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
|