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Searched refs:SUBC (Results 1 – 25 of 39) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/
Dsub128.ll1 ;test for SUBC and SUBE expansion
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h208 ADDC, SUBC, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h214 ADDC, SUBC, enumerator
/external/llvm/lib/Target/Mips/
DMips16ISelDAGToDAG.cpp200 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in trySelect()
DMipsSEISelDAGToDAG.cpp246 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelDAGToDAG.cpp214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in Select()
/external/pcre/dist2/src/sljit/
DsljitNativeSPARC_32.c106 …return push_inst(compiler, SUBC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
DsljitNativeSPARC_common.c161 #define SUBC (OPC1(0x2) | OPC3(0x0c)) macro
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h76 SUBC, // Sub with carry enumerator
DARMISelLowering.cpp568 setOperationAction(ISD::SUBC, MVT::i32, Custom); in ARMTargetLowering()
846 case ARMISD::SUBC: return "ARMISD::SUBC"; in getTargetNodeName()
4880 case ISD::SUBC: Opc = ARMISD::SUBC; break; in LowerADDC_ADDE_SUBC_SUBE()
4984 case ISD::SUBC: in LowerOperation()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h73 SUBC, // Sub with carry enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp234 case ISD::SUBC: return "subc"; in getOperationName()
DLegalizeIntegerTypes.cpp1388 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
1743 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1753 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
1834 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
2917 SDValue LowCmp = DAG.getNode(ISD::SUBC, dl, VTList, LHSLo, RHSLo); in IntegerExpandSetCCOperands()
DTargetLowering.cpp2055 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { in SimplifySetCC() local
2059 DAG.getConstant(SUBC->getAPIntValue() - in SimplifySetCC()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp92 setOperationAction(ISD::SUBC, MVT::i64, Expand); in BPFTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1846 setOperationAction(ISD::SUBC, MVT::i8, Expand); in HexagonTargetLowering()
1847 setOperationAction(ISD::SUBC, MVT::i16, Expand); in HexagonTargetLowering()
1848 setOperationAction(ISD::SUBC, MVT::i32, Expand); in HexagonTargetLowering()
1849 setOperationAction(ISD::SUBC, MVT::i64, Expand); in HexagonTargetLowering()
1938 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO, in HexagonTargetLowering()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1143 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
1519 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1529 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUB()
1578 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUBC()
DDAGCombiner.cpp2973 if (ConstantSDNode *SUBC = in MatchRotate() local
2975 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
2990 if (ConstantSDNode *SUBC = in MatchRotate() local
2992 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
3020 if (ConstantSDNode *SUBC = in MatchRotate() local
3022 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
3034 if (ConstantSDNode *SUBC = in MatchRotate() local
3036 if (SUBC->getAPIntValue() == OpSizeInBits) { in MatchRotate()
DTargetLowering.cpp2455 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { in SimplifySetCC() local
2459 DAG.getConstant(SUBC->getAPIntValue() - in SimplifySetCC()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp104 setOperationAction(ISD::SUBC , MVT::i64, Expand); in AlphaTargetLowering()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1615 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
2931 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3079 case ISD::SUBC: in LowerOperation()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp91 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAG.td345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td395 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,

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