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Searched refs:SUBREG_TO_REG (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrExtension.td166 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
169 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
171 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
174 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
176 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
179 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
184 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
186 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
DX86InstrCompiler.td270 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
302 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
315 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
1247 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1264 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1266 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1268 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1270 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1283 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1285 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
[all …]
DX86InstrAVX512.td1338 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1339 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1345 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1346 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1549 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1550 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1554 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1555 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1808 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1809 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
[all …]
DX86ISelDAGToDAG.cpp1595 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in selectLEA64_32Addr()
1609 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64, in selectLEA64_32Addr()
2412 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
2466 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, in Select()
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td222 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
224 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
226 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
230 (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
232 (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
234 (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
255 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
257 (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
259 (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
263 (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
[all …]
DAArch64InstrInfo.td549 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
1453 (SUBREG_TO_REG (i64 0),
1458 (SUBREG_TO_REG (i64 0),
1613 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1615 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1621 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1631 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1633 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1635 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1637 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
[all …]
DAArch64FastISel.cpp1826 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
3851 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
4004 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4125 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4234 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
4293 TII.get(AArch64::SUBREG_TO_REG), Src64) in emitIntExt()
4390 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4433 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h58 SUBREG_TO_REG = 9, enumerator
/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td178 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
181 (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
187 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
190 (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp117 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) in processBlock()
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
/external/llvm/include/llvm/Target/
DTargetOpcodes.def58 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
62 HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9)
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DExpandPostRAPseudos.cpp221 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
DPeepholeOptimizer.cpp192 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in OptimizeExtInstr()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp265 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
305 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
DInstrEmitter.cpp530 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
563 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
730 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1895 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2113 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2141 POpc == TargetOpcode::SUBREG_TO_REG) { in unscheduledNode()
2576 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2943 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h809 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
850 case TargetOpcode::SUBREG_TO_REG:
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp485 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
518 if (Opc == TargetOpcode::SUBREG_TO_REG) { in EmitSubregNode()
664 Opc == TargetOpcode::SUBREG_TO_REG) { in EmitMachineNode()
DScheduleDAGRRList.cpp1786 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
2005 Opc == TargetOpcode::SUBREG_TO_REG || in UnscheduledNode()
2034 POpc == TargetOpcode::SUBREG_TO_REG) { in UnscheduledNode()
2501 Opc == TargetOpcode::SUBREG_TO_REG || in canEnableCoalescing()
2871 SuccOpc == TargetOpcode::SUBREG_TO_REG) in AddPseudoTwoAddrDeps()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h279 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCompiler.td190 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
1057 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1073 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1089 // we can use a SUBREG_TO_REG.
1091 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1203 (SUBREG_TO_REG
1211 (SUBREG_TO_REG
1364 (SUBREG_TO_REG
1398 (SUBREG_TO_REG
1405 (SUBREG_TO_REG
DX86InstrSSE.td291 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
293 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
295 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
297 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
427 // with SUBREG_TO_REG.
429 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
431 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
433 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
477 // with SUBREG_TO_REG.
479 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
[all …]
DX86InstrExtension.td139 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit

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