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1 /**********************************************************
2  * Copyright 1998-2015 VMware, Inc.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person
5  * obtaining a copy of this software and associated documentation
6  * files (the "Software"), to deal in the Software without
7  * restriction, including without limitation the rights to use, copy,
8  * modify, merge, publish, distribute, sublicense, and/or sell copies
9  * of the Software, and to permit persons to whom the Software is
10  * furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  *
24  **********************************************************/
25 
26 /*
27  * svga_reg.h --
28  *
29  *    Virtual hardware definitions for the VMware SVGA II device.
30  */
31 
32 #ifndef _SVGA_REG_H_
33 #define _SVGA_REG_H_
34 
35 #include "svga_types.h"
36 
37 /*
38  * SVGA_REG_ENABLE bit definitions.
39  */
40 typedef enum {
41    SVGA_REG_ENABLE_DISABLE = 0,
42    SVGA_REG_ENABLE_ENABLE = (1 << 0),
43    SVGA_REG_ENABLE_HIDE = (1 << 1),
44 } SvgaRegEnable;
45 
46 typedef uint32 SVGAMobId;
47 
48 /*
49  * Arbitrary and meaningless limits. Please ignore these when writing
50  * new drivers.
51  */
52 #define SVGA_MAX_WIDTH                  2560
53 #define SVGA_MAX_HEIGHT                 1600
54 #define SVGA_MAX_BITS_PER_PIXEL         32
55 #define SVGA_MAX_DEPTH                  24
56 #define SVGA_MAX_DISPLAYS               10
57 
58 /*
59  * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
60  * cursor bypass mode. This is still supported, but no new guest
61  * drivers should use it.
62  */
63 #define SVGA_CURSOR_ON_HIDE            0x0   /* Must be 0 to maintain backward compatibility */
64 #define SVGA_CURSOR_ON_SHOW            0x1   /* Must be 1 to maintain backward compatibility */
65 #define SVGA_CURSOR_ON_REMOVE_FROM_FB  0x2   /* Remove the cursor from the framebuffer because we need to see what's under it */
66 #define SVGA_CURSOR_ON_RESTORE_TO_FB   0x3   /* Put the cursor back in the framebuffer so the user can see it */
67 
68 /*
69  * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
70  * The changeMap in the monitor is proportional to this number. Therefore, we'd
71  * like to keep it as small as possible to reduce monitor overhead (using
72  * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
73  * 4k!).
74  *
75  * NB: For compatibility reasons, this value must be greater than 0xff0000.
76  *     See bug 335072.
77  */
78 #define SVGA_FB_MAX_TRACEABLE_SIZE      0x1000000
79 
80 #define SVGA_MAX_PSEUDOCOLOR_DEPTH      8
81 #define SVGA_MAX_PSEUDOCOLORS           (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
82 #define SVGA_NUM_PALETTE_REGS           (3 * SVGA_MAX_PSEUDOCOLORS)
83 
84 #define SVGA_MAGIC         0x900000UL
85 #define SVGA_MAKE_ID(ver)  (SVGA_MAGIC << 8 | (ver))
86 
87 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
88 #define SVGA_VERSION_2     2
89 #define SVGA_ID_2          SVGA_MAKE_ID(SVGA_VERSION_2)
90 
91 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
92    PALETTE_BASE has moved */
93 #define SVGA_VERSION_1     1
94 #define SVGA_ID_1          SVGA_MAKE_ID(SVGA_VERSION_1)
95 
96 /* Version 0 is the initial version */
97 #define SVGA_VERSION_0     0
98 #define SVGA_ID_0          SVGA_MAKE_ID(SVGA_VERSION_0)
99 
100 /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
101 #define SVGA_ID_INVALID    0xFFFFFFFF
102 
103 /* Port offsets, relative to BAR0 */
104 #define SVGA_INDEX_PORT         0x0
105 #define SVGA_VALUE_PORT         0x1
106 #define SVGA_BIOS_PORT          0x2
107 #define SVGA_IRQSTATUS_PORT     0x8
108 
109 /*
110  * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
111  *
112  * Interrupts are only supported when the
113  * SVGA_CAP_IRQMASK capability is present.
114  */
115 #define SVGA_IRQFLAG_ANY_FENCE            0x1    /* Any fence was passed */
116 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
117 #define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
118 #define SVGA_IRQFLAG_COMMAND_BUFFER       0x8    /* Command buffer completed */
119 #define SVGA_IRQFLAG_ERROR                0x10   /* Error while processing commands */
120 
121 /*
122  * Registers
123  */
124 
125 enum {
126    SVGA_REG_ID = 0,
127    SVGA_REG_ENABLE = 1,
128    SVGA_REG_WIDTH = 2,
129    SVGA_REG_HEIGHT = 3,
130    SVGA_REG_MAX_WIDTH = 4,
131    SVGA_REG_MAX_HEIGHT = 5,
132    SVGA_REG_DEPTH = 6,
133    SVGA_REG_BITS_PER_PIXEL = 7,       /* Current bpp in the guest */
134    SVGA_REG_PSEUDOCOLOR = 8,
135    SVGA_REG_RED_MASK = 9,
136    SVGA_REG_GREEN_MASK = 10,
137    SVGA_REG_BLUE_MASK = 11,
138    SVGA_REG_BYTES_PER_LINE = 12,
139    SVGA_REG_FB_START = 13,            /* (Deprecated) */
140    SVGA_REG_FB_OFFSET = 14,
141    SVGA_REG_VRAM_SIZE = 15,
142    SVGA_REG_FB_SIZE = 16,
143 
144    /* ID 0 implementation only had the above registers, then the palette */
145    SVGA_REG_ID_0_TOP = 17,
146 
147    SVGA_REG_CAPABILITIES = 17,
148    SVGA_REG_MEM_START = 18,           /* (Deprecated) */
149    SVGA_REG_MEM_SIZE = 19,
150    SVGA_REG_CONFIG_DONE = 20,         /* Set when memory area configured */
151    SVGA_REG_SYNC = 21,                /* See "FIFO Synchronization Registers" */
152    SVGA_REG_BUSY = 22,                /* See "FIFO Synchronization Registers" */
153    SVGA_REG_GUEST_ID = 23,            /* Set guest OS identifier */
154    SVGA_REG_CURSOR_ID = 24,           /* (Deprecated) */
155    SVGA_REG_CURSOR_X = 25,            /* (Deprecated) */
156    SVGA_REG_CURSOR_Y = 26,            /* (Deprecated) */
157    SVGA_REG_CURSOR_ON = 27,           /* (Deprecated) */
158    SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
159    SVGA_REG_SCRATCH_SIZE = 29,        /* Number of scratch registers */
160    SVGA_REG_MEM_REGS = 30,            /* Number of FIFO registers */
161    SVGA_REG_NUM_DISPLAYS = 31,        /* (Deprecated) */
162    SVGA_REG_PITCHLOCK = 32,           /* Fixed pitch for all modes */
163    SVGA_REG_IRQMASK = 33,             /* Interrupt mask */
164 
165    /* Legacy multi-monitor support */
166    SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
167    SVGA_REG_DISPLAY_ID = 35,        /* Display ID for the following display attributes */
168    SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
169    SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
170    SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
171    SVGA_REG_DISPLAY_WIDTH = 39,     /* The display's width */
172    SVGA_REG_DISPLAY_HEIGHT = 40,    /* The display's height */
173 
174    /* See "Guest memory regions" below. */
175    SVGA_REG_GMR_ID = 41,
176    SVGA_REG_GMR_DESCRIPTOR = 42,
177    SVGA_REG_GMR_MAX_IDS = 43,
178    SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
179 
180    SVGA_REG_TRACES = 45,            /* Enable trace-based updates even when FIFO is on */
181    SVGA_REG_GMRS_MAX_PAGES = 46,    /* Maximum number of 4KB pages for all GMRs */
182    SVGA_REG_MEMORY_SIZE = 47,       /* Total dedicated device memory excluding FIFO */
183    SVGA_REG_COMMAND_LOW = 48,       /* Lower 32 bits and submits commands */
184    SVGA_REG_COMMAND_HIGH = 49,      /* Upper 32 bits of command buffer PA */
185    SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,   /* Max primary memory */
186    SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
187    SVGA_REG_DEV_CAP = 52,           /* Write dev cap index, read value */
188    SVGA_REG_CMD_PREPEND_LOW = 53,
189    SVGA_REG_iCMD_PREPEND_HIGH = 54,
190    SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
191    SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
192    SVGA_REG_MOB_MAX_SIZE = 57,
193    SVGA_REG_TOP = 58,               /* Must be 1 more than the last register */
194 
195    SVGA_PALETTE_BASE = 1024,        /* Base of SVGA color map */
196    /* Next 768 (== 256*3) registers exist for colormap */
197    SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
198                                     /* Base of scratch registers */
199    /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
200       First 4 are reserved for VESA BIOS Extension; any remaining are for
201       the use of the current SVGA driver. */
202 };
203 
204 /*
205  * Guest memory regions (GMRs):
206  *
207  * This is a new memory mapping feature available in SVGA devices
208  * which have the SVGA_CAP_GMR bit set. Previously, there were two
209  * fixed memory regions available with which to share data between the
210  * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
211  * are our name for an extensible way of providing arbitrary DMA
212  * buffers for use between the driver and the SVGA device. They are a
213  * new alternative to framebuffer memory, usable for both 2D and 3D
214  * graphics operations.
215  *
216  * Since GMR mapping must be done synchronously with guest CPU
217  * execution, we use a new pair of SVGA registers:
218  *
219  *   SVGA_REG_GMR_ID --
220  *
221  *     Read/write.
222  *     This register holds the 32-bit ID (a small positive integer)
223  *     of a GMR to create, delete, or redefine. Writing this register
224  *     has no side-effects.
225  *
226  *   SVGA_REG_GMR_DESCRIPTOR --
227  *
228  *     Write-only.
229  *     Writing this register will create, delete, or redefine the GMR
230  *     specified by the above ID register. If this register is zero,
231  *     the GMR is deleted. Any pointers into this GMR (including those
232  *     currently being processed by FIFO commands) will be
233  *     synchronously invalidated.
234  *
235  *     If this register is nonzero, it must be the physical page
236  *     number (PPN) of a data structure which describes the physical
237  *     layout of the memory region this GMR should describe. The
238  *     descriptor structure will be read synchronously by the SVGA
239  *     device when this register is written. The descriptor need not
240  *     remain allocated for the lifetime of the GMR.
241  *
242  *     The guest driver should write SVGA_REG_GMR_ID first, then
243  *     SVGA_REG_GMR_DESCRIPTOR.
244  *
245  *   SVGA_REG_GMR_MAX_IDS --
246  *
247  *     Read-only.
248  *     The SVGA device may choose to support a maximum number of
249  *     user-defined GMR IDs. This register holds the number of supported
250  *     IDs. (The maximum supported ID plus 1)
251  *
252  *   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
253  *
254  *     Read-only.
255  *     The SVGA device may choose to put a limit on the total number
256  *     of SVGAGuestMemDescriptor structures it will read when defining
257  *     a single GMR.
258  *
259  * The descriptor structure is an array of SVGAGuestMemDescriptor
260  * structures. Each structure may do one of three things:
261  *
262  *   - Terminate the GMR descriptor list.
263  *     (ppn==0, numPages==0)
264  *
265  *   - Add a PPN or range of PPNs to the GMR's virtual address space.
266  *     (ppn != 0, numPages != 0)
267  *
268  *   - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
269  *     support multi-page GMR descriptor tables without forcing the
270  *     driver to allocate physically contiguous memory.
271  *     (ppn != 0, numPages == 0)
272  *
273  * Note that each physical page of SVGAGuestMemDescriptor structures
274  * can describe at least 2MB of guest memory. If the driver needs to
275  * use more than one page of descriptor structures, it must use one of
276  * its SVGAGuestMemDescriptors to point to an additional page.  The
277  * device will never automatically cross a page boundary.
278  *
279  * Once the driver has described a GMR, it is immediately available
280  * for use via any FIFO command that uses an SVGAGuestPtr structure.
281  * These pointers include a GMR identifier plus an offset into that
282  * GMR.
283  *
284  * The driver must check the SVGA_CAP_GMR bit before using the GMR
285  * registers.
286  */
287 
288 /*
289  * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
290  * memory as well.  In the future, these IDs could even be used to
291  * allow legacy memory regions to be redefined by the guest as GMRs.
292  *
293  * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
294  * is being phased out. Please try to use user-defined GMRs whenever
295  * possible.
296  */
297 #define SVGA_GMR_NULL         ((uint32) -1)
298 #define SVGA_GMR_FRAMEBUFFER  ((uint32) -2)  // Guest Framebuffer (GFB)
299 
300 typedef
301 struct SVGAGuestMemDescriptor {
302    uint32 ppn;
303    uint32 numPages;
304 } SVGAGuestMemDescriptor;
305 
306 typedef
307 struct SVGAGuestPtr {
308    uint32 gmrId;
309    uint32 offset;
310 } SVGAGuestPtr;
311 
312 /*
313  * Register based command buffers --
314  *
315  * Provide an SVGA device interface that allows the guest to submit
316  * command buffers to the SVGA device through an SVGA device register.
317  * The metadata for each command buffer is contained in the
318  * SVGACBHeader structure along with the return status codes.
319  *
320  * The SVGA device supports command buffers if
321  * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register.  The
322  * fifo must be enabled for command buffers to be submitted.
323  *
324  * Command buffers are submitted when the guest writing the 64 byte
325  * aligned physical address into the SVGA_REG_COMMAND_LOW and
326  * SVGA_REG_COMMAND_HIGH.  SVGA_REG_COMMAND_HIGH contains the upper 32
327  * bits of the physical address.  SVGA_REG_COMMAND_LOW contains the
328  * lower 32 bits of the physical address, since the command buffer
329  * headers are required to be 64 byte aligned the lower 6 bits are
330  * used for the SVGACBContext value.  Writing to SVGA_REG_COMMAND_LOW
331  * submits the command buffer to the device and queues it for
332  * execution.  The SVGA device supports at least
333  * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
334  * per context and if that limit is reached the device will write the
335  * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
336  * buffer header synchronously and not raise any IRQs.
337  *
338  * It is invalid to submit a command buffer without a valid physical
339  * address and results are undefined.
340  *
341  * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
342  * will be supported.  If a larger command buffer is submitted results
343  * are unspecified and the device will either complete the command
344  * buffer or return an error.
345  *
346  * The device guarantees that any individual command in a command
347  * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
348  * enough to fit a 64x64 color-cursor definition.  If the command is
349  * too large the device is allowed to process the command or return an
350  * error.
351  *
352  * The device context is a special SVGACBContext that allows for
353  * synchronous register like accesses with the flexibility of
354  * commands.  There is a different command set defined by
355  * SVGADeviceContextCmdId.  The commands in each command buffer is not
356  * allowed to straddle physical pages.
357  */
358 
359 #define SVGA_CB_MAX_SIZE (512 * 1024)  // 512 KB
360 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
361 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
362 
363 #define SVGA_CB_CONTEXT_MASK 0x3f
364 typedef enum {
365    SVGA_CB_CONTEXT_DEVICE = 0x3f,
366    SVGA_CB_CONTEXT_0      = 0x0,
367    SVGA_CB_CONTEXT_MAX    = 0x1,
368 } SVGACBContext;
369 
370 
371 typedef enum {
372    /*
373     * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
374     * field before submitting the command buffer header, the host will
375     * change the value when it is done with the command buffer.
376     */
377    SVGA_CB_STATUS_NONE             = 0,
378 
379    /*
380     * Written by the host when a command buffer completes successfully.
381     * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
382     * the SVGA_CB_FLAG_NO_IRQ flag is set.
383     */
384    SVGA_CB_STATUS_COMPLETED        = 1,
385 
386    /*
387     * Written by the host synchronously with the command buffer
388     * submission to indicate the command buffer was not submitted.  No
389     * IRQ is raised.
390     */
391    SVGA_CB_STATUS_QUEUE_FULL       = 2,
392 
393    /*
394     * Written by the host when an error was detected parsing a command
395     * in the command buffer, errorOffset is written to contain the
396     * offset to the first byte of the failing command.  The device
397     * raises the IRQ with both SVGA_IRQFLAG_ERROR and
398     * SVGA_IRQFLAG_COMMAND_BUFFER.  Some of the commands may have been
399     * processed.
400     */
401    SVGA_CB_STATUS_COMMAND_ERROR    = 3,
402 
403    /*
404     * Written by the host if there is an error parsing the command
405     * buffer header.  The device raises the IRQ with both
406     * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER.  The device
407     * did not processes any of the command buffer.
408     */
409    SVGA_CB_STATUS_CB_HEADER_ERROR  = 4,
410 
411    /*
412     * Written by the host if the guest requested the host to preempt
413     * the command buffer.  The device will not raise any IRQs and the
414     * command buffer was not processed.
415     */
416    SVGA_CB_STATUS_PREEMPTED        = 5,
417 } SVGACBStatus;
418 
419 typedef enum {
420    SVGA_CB_FLAG_NONE     = 0,
421    SVGA_CB_FLAG_NO_IRQ   = 1 << 0,
422 } SVGACBFlags;
423 
424 typedef
425 struct {
426    volatile SVGACBStatus status;
427    volatile uint32 errorOffset;
428    uint64 id;
429    SVGACBFlags flags;
430    uint32 length;
431    union {
432       PA pa;
433    } ptr;
434    uint32 mustBeZero[8];
435 } SVGACBHeader;
436 
437 typedef enum {
438    SVGA_DC_CMD_NOP                   = 0,
439    SVGA_DC_CMD_START_STOP_CONTEXT    = 1,
440    SVGA_DC_CMD_PREEMPT               = 2,
441    SVGA_DC_CMD_MAX                   = 3,
442    SVGA_DC_CMD_FORCE_UINT            = MAX_UINT32,
443 } SVGADeviceContextCmdId;
444 
445 typedef struct {
446    uint32 enable;
447    SVGACBContext context;
448 } SVGADCCmdStartStop;
449 
450 /*
451  * SVGADCCmdPreempt --
452  *
453  * This command allows the guest to request that all command buffers
454  * on the specified context be preempted that can be.  After execution
455  * of this command all command buffers that were preempted will
456  * already have SVGA_CB_STATUS_PREEMPTED written into the status
457  * field.  The device might still be processing a command buffer,
458  * assuming execution of it started before the preemption request was
459  * received.  Specifying the ignoreIDZero flag to TRUE will cause the
460  * device to not preempt command buffers with the id field in the
461  * command buffer header set to zero.
462  */
463 
464 typedef struct {
465    SVGACBContext context;
466    uint32 ignoreIDZero;
467 } SVGADCCmdPreempt;
468 
469 
470 /*
471  * SVGAGMRImageFormat --
472  *
473  *    This is a packed representation of the source 2D image format
474  *    for a GMR-to-screen blit. Currently it is defined as an encoding
475  *    of the screen's color depth and bits-per-pixel, however, 16 bits
476  *    are reserved for future use to identify other encodings (such as
477  *    RGBA or higher-precision images).
478  *
479  *    Currently supported formats:
480  *
481  *       bpp depth  Format Name
482  *       --- -----  -----------
483  *        32    24  32-bit BGRX
484  *        24    24  24-bit BGR
485  *        16    16  RGB 5-6-5
486  *        16    15  RGB 5-5-5
487  *
488  */
489 
490 typedef struct SVGAGMRImageFormat {
491    union {
492       struct {
493          uint32 bitsPerPixel : 8;
494          uint32 colorDepth   : 8;
495 	 uint32 reserved     : 16;  /* Must be zero */
496       };
497 
498       uint32 value;
499    };
500 } SVGAGMRImageFormat;
501 
502 typedef
503 struct SVGAGuestImage {
504    SVGAGuestPtr         ptr;
505 
506    /*
507     * A note on interpretation of pitch: This value of pitch is the
508     * number of bytes between vertically adjacent image
509     * blocks. Normally this is the number of bytes between the first
510     * pixel of two adjacent scanlines. With compressed textures,
511     * however, this may represent the number of bytes between
512     * compression blocks rather than between rows of pixels.
513     *
514     * XXX: Compressed textures currently must be tightly packed in guest memory.
515     *
516     * If the image is 1-dimensional, pitch is ignored.
517     *
518     * If 'pitch' is zero, the SVGA3D device calculates a pitch value
519     * assuming each row of blocks is tightly packed.
520     */
521    uint32 pitch;
522 } SVGAGuestImage;
523 
524 /*
525  * SVGAColorBGRX --
526  *
527  *    A 24-bit color format (BGRX), which does not depend on the
528  *    format of the legacy guest framebuffer (GFB) or the current
529  *    GMRFB state.
530  */
531 
532 typedef struct SVGAColorBGRX {
533    union {
534       struct {
535          uint32 b : 8;
536          uint32 g : 8;
537          uint32 r : 8;
538 	     uint32 x : 8;  /* Unused */
539       };
540 
541       uint32 value;
542    };
543 } SVGAColorBGRX;
544 
545 
546 /*
547  * SVGASignedRect --
548  * SVGASignedPoint --
549  *
550  *    Signed rectangle and point primitives. These are used by the new
551  *    2D primitives for drawing to Screen Objects, which can occupy a
552  *    signed virtual coordinate space.
553  *
554  *    SVGASignedRect specifies a half-open interval: the (left, top)
555  *    pixel is part of the rectangle, but the (right, bottom) pixel is
556  *    not.
557  */
558 
559 typedef
560 struct {
561    int32  left;
562    int32  top;
563    int32  right;
564    int32  bottom;
565 } SVGASignedRect;
566 
567 typedef
568 struct {
569    int32  x;
570    int32  y;
571 } SVGASignedPoint;
572 
573 
574 /*
575  * SVGA Device Capabilities
576  *
577  * Note the holes in the bitfield. Missing bits have been deprecated,
578  * and must not be reused. Those capabilities will never be reported
579  * by new versions of the SVGA device.
580  *
581  * XXX: Add longer descriptions for each capability, including a list
582  *      of the new features that each capability provides.
583  *
584  * SVGA_CAP_IRQMASK --
585  *    Provides device interrupts.  Adds device register SVGA_REG_IRQMASK
586  *    to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
587  *    set/clear pending interrupts.
588  *
589  * SVGA_CAP_GMR --
590  *    Provides synchronous mapping of guest memory regions (GMR).
591  *    Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
592  *    SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
593  *
594  * SVGA_CAP_TRACES --
595  *    Allows framebuffer trace-based updates even when FIFO is enabled.
596  *    Adds device register SVGA_REG_TRACES.
597  *
598  * SVGA_CAP_GMR2 --
599  *    Provides asynchronous commands to define and remap guest memory
600  *    regions.  Adds device registers SVGA_REG_GMRS_MAX_PAGES and
601  *    SVGA_REG_MEMORY_SIZE.
602  *
603  * SVGA_CAP_SCREEN_OBJECT_2 --
604  *    Allow screen object support, and require backing stores from the
605  *    guest for each screen object.
606  *
607  * SVGA_CAP_COMMAND_BUFFERS --
608  *    Enable register based command buffer submission.
609  *
610  * SVGA_CAP_DEAD1 --
611  *    This cap was incorrectly used by old drivers and should not be
612  *    reused.
613  *
614  * SVGA_CAP_CMD_BUFFERS_2 --
615  *    Enable support for the prepend command buffer submision
616  *    registers.  SVGA_REG_CMD_PREPEND_LOW and
617  *    SVGA_REG_CMD_PREPEND_HIGH.
618  *
619  * SVGA_CAP_GBOBJECTS --
620  *    Enable guest-backed objects and surfaces.
621  *
622  * SVGA_CAP_CMD_BUFFERS_3 --
623  *    Enable support for command buffers in a mob.
624  */
625 
626 #define SVGA_CAP_NONE               0x00000000
627 #define SVGA_CAP_RECT_COPY          0x00000002
628 #define SVGA_CAP_CURSOR             0x00000020
629 #define SVGA_CAP_CURSOR_BYPASS      0x00000040
630 #define SVGA_CAP_CURSOR_BYPASS_2    0x00000080
631 #define SVGA_CAP_8BIT_EMULATION     0x00000100
632 #define SVGA_CAP_ALPHA_CURSOR       0x00000200
633 #define SVGA_CAP_3D                 0x00004000
634 #define SVGA_CAP_EXTENDED_FIFO      0x00008000
635 #define SVGA_CAP_MULTIMON           0x00010000
636 #define SVGA_CAP_PITCHLOCK          0x00020000
637 #define SVGA_CAP_IRQMASK            0x00040000
638 #define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000
639 #define SVGA_CAP_GMR                0x00100000
640 #define SVGA_CAP_TRACES             0x00200000
641 #define SVGA_CAP_GMR2               0x00400000
642 #define SVGA_CAP_SCREEN_OBJECT_2    0x00800000
643 #define SVGA_CAP_COMMAND_BUFFERS    0x01000000
644 #define SVGA_CAP_DEAD1              0x02000000
645 #define SVGA_CAP_CMD_BUFFERS_2      0x04000000
646 #define SVGA_CAP_GBOBJECTS          0x08000000
647 #define SVGA_CAP_CMD_BUFFERS_3      0x10000000
648 
649 #define SVGA_CAP_CMD_RESERVED       0x80000000
650 
651 
652 /*
653  * The Guest can optionally read some SVGA device capabilities through
654  * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
655  * the SVGA device is initialized.  The type of capability the guest
656  * is requesting from the SVGABackdoorCapType enum should be placed in
657  * the upper 16 bits of the backdoor command id (ECX).  On success the
658  * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
659  * the requested capability.  If the command is not supported then EBX
660  * will be left unchanged and EAX will be set to -1.  Because it is
661  * possible that -1 is the value of the requested cap the correct way
662  * to check if the command was successful is to check if EBX was changed
663  * to BDOOR_MAGIC making sure to initialize the register to something
664  * else first.
665  */
666 
667 typedef enum {
668    SVGABackdoorCapDeviceCaps = 0,
669    SVGABackdoorCapFifoCaps = 1,
670    SVGABackdoorCap3dHWVersion = 2,
671    SVGABackdoorCapMax = 3,
672 } SVGABackdoorCapType;
673 
674 
675 /*
676  * FIFO register indices.
677  *
678  * The FIFO is a chunk of device memory mapped into guest physmem.  It
679  * is always treated as 32-bit words.
680  *
681  * The guest driver gets to decide how to partition it between
682  * - FIFO registers (there are always at least 4, specifying where the
683  *   following data area is and how much data it contains; there may be
684  *   more registers following these, depending on the FIFO protocol
685  *   version in use)
686  * - FIFO data, written by the guest and slurped out by the VMX.
687  * These indices are 32-bit word offsets into the FIFO.
688  */
689 
690 enum {
691    /*
692     * Block 1 (basic registers): The originally defined FIFO registers.
693     * These exist and are valid for all versions of the FIFO protocol.
694     */
695 
696    SVGA_FIFO_MIN = 0,
697    SVGA_FIFO_MAX,       /* The distance from MIN to MAX must be at least 10K */
698    SVGA_FIFO_NEXT_CMD,
699    SVGA_FIFO_STOP,
700 
701    /*
702     * Block 2 (extended registers): Mandatory registers for the extended
703     * FIFO.  These exist if the SVGA caps register includes
704     * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
705     * associated capability bit is enabled.
706     *
707     * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
708     * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
709     * This means that the guest has to test individually (in most cases
710     * using FIFO caps) for the presence of registers after this; the VMX
711     * can define "extended FIFO" to mean whatever it wants, and currently
712     * won't enable it unless there's room for that set and much more.
713     */
714 
715    SVGA_FIFO_CAPABILITIES = 4,
716    SVGA_FIFO_FLAGS,
717    /* Valid with SVGA_FIFO_CAP_FENCE: */
718    SVGA_FIFO_FENCE,
719 
720    /*
721     * Block 3a (optional extended registers): Additional registers for the
722     * extended FIFO, whose presence isn't actually implied by
723     * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
724     * leave room for them.
725     *
726     * These in block 3a, the VMX currently considers mandatory for the
727     * extended FIFO.
728     */
729 
730    /* Valid if exists (i.e. if extended FIFO enabled): */
731    SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
732    /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
733    SVGA_FIFO_PITCHLOCK,
734 
735    /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
736    SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
737    SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
738    SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
739    SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
740    SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
741 
742    /* Valid with SVGA_FIFO_CAP_RESERVE: */
743    SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
744 
745    /*
746     * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
747     *
748     * By default this is SVGA_ID_INVALID, to indicate that the cursor
749     * coordinates are specified relative to the virtual root. If this
750     * is set to a specific screen ID, cursor position is reinterpreted
751     * as a signed offset relative to that screen's origin.
752     */
753    SVGA_FIFO_CURSOR_SCREEN_ID,
754 
755    /*
756     * Valid with SVGA_FIFO_CAP_DEAD
757     *
758     * An arbitrary value written by the host, drivers should not use it.
759     */
760    SVGA_FIFO_DEAD,
761 
762    /*
763     * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
764     *
765     * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
766     * on platforms that can enforce graphics resource limits.
767     */
768    SVGA_FIFO_3D_HWVERSION_REVISED,
769 
770    /*
771     * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
772     * registers, but this must be done carefully and with judicious use of
773     * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
774     * enough to tell you whether the register exists: we've shipped drivers
775     * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
776     * the earlier ones.  The actual order of introduction was:
777     * - PITCHLOCK
778     * - 3D_CAPS
779     * - CURSOR_* (cursor bypass 3)
780     * - RESERVED
781     * So, code that wants to know whether it can use any of the
782     * aforementioned registers, or anything else added after PITCHLOCK and
783     * before 3D_CAPS, needs to reason about something other than
784     * SVGA_FIFO_MIN.
785     */
786 
787    /*
788     * 3D caps block space; valid with 3D hardware version >=
789     * SVGA3D_HWVERSION_WS6_B1.
790     */
791    SVGA_FIFO_3D_CAPS      = 32,
792    SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
793 
794    /*
795     * End of VMX's current definition of "extended-FIFO registers".
796     * Registers before here are always enabled/disabled as a block; either
797     * the extended FIFO is enabled and includes all preceding registers, or
798     * it's disabled entirely.
799     *
800     * Block 3b (truly optional extended registers): Additional registers for
801     * the extended FIFO, which the VMX already knows how to enable and
802     * disable with correct granularity.
803     *
804     * Registers after here exist if and only if the guest SVGA driver
805     * sets SVGA_FIFO_MIN high enough to leave room for them.
806     */
807 
808    /* Valid if register exists: */
809    SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
810    SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
811    SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
812 
813    /*
814     * Always keep this last.  This defines the maximum number of
815     * registers we know about.  At power-on, this value is placed in
816     * the SVGA_REG_MEM_REGS register, and we expect the guest driver
817     * to allocate this much space in FIFO memory for registers.
818     */
819     SVGA_FIFO_NUM_REGS
820 };
821 
822 
823 /*
824  * Definition of registers included in extended FIFO support.
825  *
826  * The guest SVGA driver gets to allocate the FIFO between registers
827  * and data.  It must always allocate at least 4 registers, but old
828  * drivers stopped there.
829  *
830  * The VMX will enable extended FIFO support if and only if the guest
831  * left enough room for all registers defined as part of the mandatory
832  * set for the extended FIFO.
833  *
834  * Note that the guest drivers typically allocate the FIFO only at
835  * initialization time, not at mode switches, so it's likely that the
836  * number of FIFO registers won't change without a reboot.
837  *
838  * All registers less than this value are guaranteed to be present if
839  * svgaUser->fifo.extended is set. Any later registers must be tested
840  * individually for compatibility at each use (in the VMX).
841  *
842  * This value is used only by the VMX, so it can change without
843  * affecting driver compatibility; keep it that way?
844  */
845 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS  (SVGA_FIFO_3D_CAPS_LAST + 1)
846 
847 
848 /*
849  * FIFO Synchronization Registers
850  *
851  *  This explains the relationship between the various FIFO
852  *  sync-related registers in IOSpace and in FIFO space.
853  *
854  *  SVGA_REG_SYNC --
855  *
856  *       The SYNC register can be used in two different ways by the guest:
857  *
858  *         1. If the guest wishes to fully sync (drain) the FIFO,
859  *            it will write once to SYNC then poll on the BUSY
860  *            register. The FIFO is sync'ed once BUSY is zero.
861  *
862  *         2. If the guest wants to asynchronously wake up the host,
863  *            it will write once to SYNC without polling on BUSY.
864  *            Ideally it will do this after some new commands have
865  *            been placed in the FIFO, and after reading a zero
866  *            from SVGA_FIFO_BUSY.
867  *
868  *       (1) is the original behaviour that SYNC was designed to
869  *       support.  Originally, a write to SYNC would implicitly
870  *       trigger a read from BUSY. This causes us to synchronously
871  *       process the FIFO.
872  *
873  *       This behaviour has since been changed so that writing SYNC
874  *       will *not* implicitly cause a read from BUSY. Instead, it
875  *       makes a channel call which asynchronously wakes up the MKS
876  *       thread.
877  *
878  *       New guests can use this new behaviour to implement (2)
879  *       efficiently. This lets guests get the host's attention
880  *       without waiting for the MKS to poll, which gives us much
881  *       better CPU utilization on SMP hosts and on UP hosts while
882  *       we're blocked on the host GPU.
883  *
884  *       Old guests shouldn't notice the behaviour change. SYNC was
885  *       never guaranteed to process the entire FIFO, since it was
886  *       bounded to a particular number of CPU cycles. Old guests will
887  *       still loop on the BUSY register until the FIFO is empty.
888  *
889  *       Writing to SYNC currently has the following side-effects:
890  *
891  *         - Sets SVGA_REG_BUSY to TRUE (in the monitor)
892  *         - Asynchronously wakes up the MKS thread for FIFO processing
893  *         - The value written to SYNC is recorded as a "reason", for
894  *           stats purposes.
895  *
896  *       If SVGA_FIFO_BUSY is available, drivers are advised to only
897  *       write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
898  *       SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
899  *       eventually set SVGA_FIFO_BUSY on its own, but this approach
900  *       lets the driver avoid sending multiple asynchronous wakeup
901  *       messages to the MKS thread.
902  *
903  *  SVGA_REG_BUSY --
904  *
905  *       This register is set to TRUE when SVGA_REG_SYNC is written,
906  *       and it reads as FALSE when the FIFO has been completely
907  *       drained.
908  *
909  *       Every read from this register causes us to synchronously
910  *       process FIFO commands. There is no guarantee as to how many
911  *       commands each read will process.
912  *
913  *       CPU time spent processing FIFO commands will be billed to
914  *       the guest.
915  *
916  *       New drivers should avoid using this register unless they
917  *       need to guarantee that the FIFO is completely drained. It
918  *       is overkill for performing a sync-to-fence. Older drivers
919  *       will use this register for any type of synchronization.
920  *
921  *  SVGA_FIFO_BUSY --
922  *
923  *       This register is a fast way for the guest driver to check
924  *       whether the FIFO is already being processed. It reads and
925  *       writes at normal RAM speeds, with no monitor intervention.
926  *
927  *       If this register reads as TRUE, the host is guaranteeing that
928  *       any new commands written into the FIFO will be noticed before
929  *       the MKS goes back to sleep.
930  *
931  *       If this register reads as FALSE, no such guarantee can be
932  *       made.
933  *
934  *       The guest should use this register to quickly determine
935  *       whether or not it needs to wake up the host. If the guest
936  *       just wrote a command or group of commands that it would like
937  *       the host to begin processing, it should:
938  *
939  *         1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
940  *            action is necessary.
941  *
942  *         2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
943  *            code that we've already sent a SYNC to the host and we
944  *            don't need to send a duplicate.
945  *
946  *         3. Write a reason to SVGA_REG_SYNC. This will send an
947  *            asynchronous wakeup to the MKS thread.
948  */
949 
950 
951 /*
952  * FIFO Capabilities
953  *
954  *      Fence -- Fence register and command are supported
955  *      Accel Front -- Front buffer only commands are supported
956  *      Pitch Lock -- Pitch lock register is supported
957  *      Video -- SVGA Video overlay units are supported
958  *      Escape -- Escape command is supported
959  *
960  * XXX: Add longer descriptions for each capability, including a list
961  *      of the new features that each capability provides.
962  *
963  * SVGA_FIFO_CAP_SCREEN_OBJECT --
964  *
965  *    Provides dynamic multi-screen rendering, for improved Unity and
966  *    multi-monitor modes. With Screen Object, the guest can
967  *    dynamically create and destroy 'screens', which can represent
968  *    Unity windows or virtual monitors. Screen Object also provides
969  *    strong guarantees that DMA operations happen only when
970  *    guest-initiated. Screen Object deprecates the BAR1 guest
971  *    framebuffer (GFB) and all commands that work only with the GFB.
972  *
973  *    New registers:
974  *       FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
975  *
976  *    New 2D commands:
977  *       DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
978  *       BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
979  *
980  *    New 3D commands:
981  *       BLIT_SURFACE_TO_SCREEN
982  *
983  *    New guarantees:
984  *
985  *       - The host will not read or write guest memory, including the GFB,
986  *         except when explicitly initiated by a DMA command.
987  *
988  *       - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
989  *         is guaranteed to complete before any subsequent FENCEs.
990  *
991  *       - All legacy commands which affect a Screen (UPDATE, PRESENT,
992  *         PRESENT_READBACK) as well as new Screen blit commands will
993  *         all behave consistently as blits, and memory will be read
994  *         or written in FIFO order.
995  *
996  *         For example, if you PRESENT from one SVGA3D surface to multiple
997  *         places on the screen, the data copied will always be from the
998  *         SVGA3D surface at the time the PRESENT was issued in the FIFO.
999  *         This was not necessarily true on devices without Screen Object.
1000  *
1001  *         This means that on devices that support Screen Object, the
1002  *         PRESENT_READBACK command should not be necessary unless you
1003  *         actually want to read back the results of 3D rendering into
1004  *         system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
1005  *         command provides a strict superset of functionality.)
1006  *
1007  *       - When a screen is resized, either using Screen Object commands or
1008  *         legacy multimon registers, its contents are preserved.
1009  *
1010  * SVGA_FIFO_CAP_GMR2 --
1011  *
1012  *    Provides new commands to define and remap guest memory regions (GMR).
1013  *
1014  *    New 2D commands:
1015  *       DEFINE_GMR2, REMAP_GMR2.
1016  *
1017  * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1018  *
1019  *    Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1020  *    This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1021  *    that enforce graphics resource limits.  This allows the platform
1022  *    to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1023  *    drivers that do not limit their resources.
1024  *
1025  *    Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1026  *    are codependent (and thus we use a single capability bit).
1027  *
1028  * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1029  *
1030  *    Modifies the DEFINE_SCREEN command to include a guest provided
1031  *    backing store in GMR memory and the bytesPerLine for the backing
1032  *    store.  This capability requires the use of a backing store when
1033  *    creating screen objects.  However if SVGA_FIFO_CAP_SCREEN_OBJECT
1034  *    is present then backing stores are optional.
1035  *
1036  * SVGA_FIFO_CAP_DEAD --
1037  *
1038  *    Drivers should not use this cap bit.  This cap bit can not be
1039  *    reused since some hosts already expose it.
1040  */
1041 
1042 #define SVGA_FIFO_CAP_NONE                  0
1043 #define SVGA_FIFO_CAP_FENCE             (1<<0)
1044 #define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
1045 #define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
1046 #define SVGA_FIFO_CAP_VIDEO             (1<<3)
1047 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
1048 #define SVGA_FIFO_CAP_ESCAPE            (1<<5)
1049 #define SVGA_FIFO_CAP_RESERVE           (1<<6)
1050 #define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
1051 #define SVGA_FIFO_CAP_GMR2              (1<<8)
1052 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED  SVGA_FIFO_CAP_GMR2
1053 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2   (1<<9)
1054 #define SVGA_FIFO_CAP_DEAD              (1<<10)
1055 
1056 
1057 /*
1058  * FIFO Flags
1059  *
1060  *      Accel Front -- Driver should use front buffer only commands
1061  */
1062 
1063 #define SVGA_FIFO_FLAG_NONE                 0
1064 #define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
1065 #define SVGA_FIFO_FLAG_RESERVED        (1<<31) /* Internal use only */
1066 
1067 /*
1068  * FIFO reservation sentinel value
1069  */
1070 
1071 #define SVGA_FIFO_RESERVED_UNKNOWN      0xffffffff
1072 
1073 
1074 /*
1075  * Video overlay support
1076  */
1077 
1078 #define SVGA_NUM_OVERLAY_UNITS 32
1079 
1080 
1081 /*
1082  * Video capabilities that the guest is currently using
1083  */
1084 
1085 #define SVGA_VIDEO_FLAG_COLORKEY        0x0001
1086 
1087 
1088 /*
1089  * Offsets for the video overlay registers
1090  */
1091 
1092 enum {
1093    SVGA_VIDEO_ENABLED = 0,
1094    SVGA_VIDEO_FLAGS,
1095    SVGA_VIDEO_DATA_OFFSET,
1096    SVGA_VIDEO_FORMAT,
1097    SVGA_VIDEO_COLORKEY,
1098    SVGA_VIDEO_SIZE,          /* Deprecated */
1099    SVGA_VIDEO_WIDTH,
1100    SVGA_VIDEO_HEIGHT,
1101    SVGA_VIDEO_SRC_X,
1102    SVGA_VIDEO_SRC_Y,
1103    SVGA_VIDEO_SRC_WIDTH,
1104    SVGA_VIDEO_SRC_HEIGHT,
1105    SVGA_VIDEO_DST_X,         /* Signed int32 */
1106    SVGA_VIDEO_DST_Y,         /* Signed int32 */
1107    SVGA_VIDEO_DST_WIDTH,
1108    SVGA_VIDEO_DST_HEIGHT,
1109    SVGA_VIDEO_PITCH_1,
1110    SVGA_VIDEO_PITCH_2,
1111    SVGA_VIDEO_PITCH_3,
1112    SVGA_VIDEO_DATA_GMRID,    /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1113    SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1114                              /* (SVGA_ID_INVALID) */
1115    SVGA_VIDEO_NUM_REGS
1116 };
1117 
1118 
1119 /*
1120  * SVGA Overlay Units
1121  *
1122  *      width and height relate to the entire source video frame.
1123  *      srcX, srcY, srcWidth and srcHeight represent subset of the source
1124  *      video frame to be displayed.
1125  */
1126 
1127 typedef struct SVGAOverlayUnit {
1128    uint32 enabled;
1129    uint32 flags;
1130    uint32 dataOffset;
1131    uint32 format;
1132    uint32 colorKey;
1133    uint32 size;
1134    uint32 width;
1135    uint32 height;
1136    uint32 srcX;
1137    uint32 srcY;
1138    uint32 srcWidth;
1139    uint32 srcHeight;
1140    int32  dstX;
1141    int32  dstY;
1142    uint32 dstWidth;
1143    uint32 dstHeight;
1144    uint32 pitches[3];
1145    uint32 dataGMRId;
1146    uint32 dstScreenId;
1147 } SVGAOverlayUnit;
1148 
1149 
1150 /*
1151  * Guest display topology
1152  *
1153  * XXX: This structure is not part of the SVGA device's interface, and
1154  * doesn't really belong here.
1155  */
1156 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1157 
1158 typedef struct SVGADisplayTopology {
1159    uint16 displayId;
1160    uint16 isPrimary;
1161    uint32 width;
1162    uint32 height;
1163    uint32 positionX;
1164    uint32 positionY;
1165 } SVGADisplayTopology;
1166 
1167 
1168 /*
1169  * SVGAScreenObject --
1170  *
1171  *    This is a new way to represent a guest's multi-monitor screen or
1172  *    Unity window. Screen objects are only supported if the
1173  *    SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1174  *
1175  *    If Screen Objects are supported, they can be used to fully
1176  *    replace the functionality provided by the framebuffer registers
1177  *    (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1178  *
1179  *    The screen object is a struct with guaranteed binary
1180  *    compatibility. New flags can be added, and the struct may grow,
1181  *    but existing fields must retain their meaning.
1182  *
1183  *    Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1184  *    a SVGAGuestPtr that is used to back the screen contents.  This
1185  *    memory must come from the GFB.  The guest is not allowed to
1186  *    access the memory and doing so will have undefined results.  The
1187  *    backing store is required to be page aligned and the size is
1188  *    padded to the next page boundry.  The number of pages is:
1189  *       (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1190  *
1191  *    The pitch in the backingStore is required to be at least large
1192  *    enough to hold a 32bbp scanline.  It is recommended that the
1193  *    driver pad bytesPerLine for a potential performance win.
1194  *
1195  *    The cloneCount field is treated as a hint from the guest that
1196  *    the user wants this display to be cloned, countCount times.  A
1197  *    value of zero means no cloning should happen.
1198  */
1199 
1200 #define SVGA_SCREEN_MUST_BE_SET     (1 << 0)
1201 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1202 #define SVGA_SCREEN_IS_PRIMARY      (1 << 1)
1203 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1204 
1205 /*
1206  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When the screen is
1207  * deactivated the base layer is defined to lose all contents and
1208  * become black.  When a screen is deactivated the backing store is
1209  * optional.  When set backingPtr and bytesPerLine will be ignored.
1210  */
1211 #define SVGA_SCREEN_DEACTIVATE  (1 << 3)
1212 
1213 /*
1214  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When this flag is set
1215  * the screen contents will be outputted as all black to the user
1216  * though the base layer contents is preserved.  The screen base layer
1217  * can still be read and written to like normal though the no visible
1218  * effect will be seen by the user.  When the flag is changed the
1219  * screen will be blanked or redrawn to the current contents as needed
1220  * without any extra commands from the driver.  This flag only has an
1221  * effect when the screen is not deactivated.
1222  */
1223 #define SVGA_SCREEN_BLANKING (1 << 4)
1224 
1225 typedef
1226 struct {
1227    uint32 structSize;   /* sizeof(SVGAScreenObject) */
1228    uint32 id;
1229    uint32 flags;
1230    struct {
1231       uint32 width;
1232       uint32 height;
1233    } size;
1234    struct {
1235       int32 x;
1236       int32 y;
1237    } root;
1238 
1239    /*
1240     * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1241     * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1242     */
1243    SVGAGuestImage backingStore;
1244 
1245    /*
1246     * The cloneCount field is treated as a hint from the guest that
1247     * the user wants this display to be cloned, cloneCount times.
1248     *
1249     * A value of zero means no cloning should happen.
1250     */
1251    uint32 cloneCount;
1252 } SVGAScreenObject;
1253 
1254 
1255 /*
1256  *  Commands in the command FIFO:
1257  *
1258  *  Command IDs defined below are used for the traditional 2D FIFO
1259  *  communication (not all commands are available for all versions of the
1260  *  SVGA FIFO protocol).
1261  *
1262  *  Note the holes in the command ID numbers: These commands have been
1263  *  deprecated, and the old IDs must not be reused.
1264  *
1265  *  Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1266  *  protocol.
1267  *
1268  *  Each command's parameters are described by the comments and
1269  *  structs below.
1270  */
1271 
1272 typedef enum {
1273    SVGA_CMD_INVALID_CMD           = 0,
1274    SVGA_CMD_UPDATE                = 1,
1275    SVGA_CMD_RECT_COPY             = 3,
1276    SVGA_CMD_RECT_ROP_COPY         = 14,
1277    SVGA_CMD_DEFINE_CURSOR         = 19,
1278    SVGA_CMD_DEFINE_ALPHA_CURSOR   = 22,
1279    SVGA_CMD_UPDATE_VERBOSE        = 25,
1280    SVGA_CMD_FRONT_ROP_FILL        = 29,
1281    SVGA_CMD_FENCE                 = 30,
1282    SVGA_CMD_ESCAPE                = 33,
1283    SVGA_CMD_DEFINE_SCREEN         = 34,
1284    SVGA_CMD_DESTROY_SCREEN        = 35,
1285    SVGA_CMD_DEFINE_GMRFB          = 36,
1286    SVGA_CMD_BLIT_GMRFB_TO_SCREEN  = 37,
1287    SVGA_CMD_BLIT_SCREEN_TO_GMRFB  = 38,
1288    SVGA_CMD_ANNOTATION_FILL       = 39,
1289    SVGA_CMD_ANNOTATION_COPY       = 40,
1290    SVGA_CMD_DEFINE_GMR2           = 41,
1291    SVGA_CMD_REMAP_GMR2            = 42,
1292    SVGA_CMD_DEAD                  = 43,
1293    SVGA_CMD_DEAD_2                = 44,
1294    SVGA_CMD_NOP                   = 45,
1295    SVGA_CMD_NOP_ERROR             = 46,
1296    SVGA_CMD_MAX
1297 } SVGAFifoCmdId;
1298 
1299 #define SVGA_CMD_MAX_DATASIZE       (256 * 1024)
1300 #define SVGA_CMD_MAX_ARGS           64
1301 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
1302 
1303 
1304 /*
1305  * SVGA_CMD_UPDATE --
1306  *
1307  *    This is a DMA transfer which copies from the Guest Framebuffer
1308  *    (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1309  *    intersect with the provided virtual rectangle.
1310  *
1311  *    This command does not support using arbitrary guest memory as a
1312  *    data source- it only works with the pre-defined GFB memory.
1313  *    This command also does not support signed virtual coordinates.
1314  *    If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1315  *    negative root x/y coordinates, the negative portion of those
1316  *    screens will not be reachable by this command.
1317  *
1318  *    This command is not necessary when using framebuffer
1319  *    traces. Traces are automatically enabled if the SVGA FIFO is
1320  *    disabled, and you may explicitly enable/disable traces using
1321  *    SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1322  *    automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1323  *
1324  *    Traces and SVGA_CMD_UPDATE are the only supported ways to render
1325  *    pseudocolor screen updates. The newer Screen Object commands
1326  *    only support true color formats.
1327  *
1328  * Availability:
1329  *    Always available.
1330  */
1331 
1332 typedef
1333 struct {
1334    uint32 x;
1335    uint32 y;
1336    uint32 width;
1337    uint32 height;
1338 } SVGAFifoCmdUpdate;
1339 
1340 
1341 /*
1342  * SVGA_CMD_RECT_COPY --
1343  *
1344  *    Perform a rectangular DMA transfer from one area of the GFB to
1345  *    another, and copy the result to any screens which intersect it.
1346  *
1347  * Availability:
1348  *    SVGA_CAP_RECT_COPY
1349  */
1350 
1351 typedef
1352 struct {
1353    uint32 srcX;
1354    uint32 srcY;
1355    uint32 destX;
1356    uint32 destY;
1357    uint32 width;
1358    uint32 height;
1359 } SVGAFifoCmdRectCopy;
1360 
1361 
1362 /*
1363  * SVGA_CMD_RECT_ROP_COPY --
1364  *
1365  *    Perform a rectangular DMA transfer from one area of the GFB to
1366  *    another, and copy the result to any screens which intersect it.
1367  *    The value of ROP may only be SVGA_ROP_COPY, and this command is
1368  *    only supported for backwards compatibility reasons.
1369  *
1370  * Availability:
1371  *    SVGA_CAP_RECT_COPY
1372  */
1373 
1374 typedef
1375 struct {
1376    uint32 srcX;
1377    uint32 srcY;
1378    uint32 destX;
1379    uint32 destY;
1380    uint32 width;
1381    uint32 height;
1382    uint32 rop;
1383 } SVGAFifoCmdRectRopCopy;
1384 
1385 
1386 /*
1387  * SVGA_CMD_DEFINE_CURSOR --
1388  *
1389  *    Provide a new cursor image, as an AND/XOR mask.
1390  *
1391  *    The recommended way to position the cursor overlay is by using
1392  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1393  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1394  *
1395  * Availability:
1396  *    SVGA_CAP_CURSOR
1397  */
1398 
1399 typedef
1400 struct {
1401    uint32 id;             /* Reserved, must be zero. */
1402    uint32 hotspotX;
1403    uint32 hotspotY;
1404    uint32 width;
1405    uint32 height;
1406    uint32 andMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1407    uint32 xorMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1408    /*
1409     * Followed by scanline data for AND mask, then XOR mask.
1410     * Each scanline is padded to a 32-bit boundary.
1411    */
1412 } SVGAFifoCmdDefineCursor;
1413 
1414 
1415 /*
1416  * SVGA_CMD_DEFINE_ALPHA_CURSOR --
1417  *
1418  *    Provide a new cursor image, in 32-bit BGRA format.
1419  *
1420  *    The recommended way to position the cursor overlay is by using
1421  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1422  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1423  *
1424  * Availability:
1425  *    SVGA_CAP_ALPHA_CURSOR
1426  */
1427 
1428 typedef
1429 struct {
1430    uint32 id;             /* Reserved, must be zero. */
1431    uint32 hotspotX;
1432    uint32 hotspotY;
1433    uint32 width;
1434    uint32 height;
1435    /* Followed by scanline data */
1436 } SVGAFifoCmdDefineAlphaCursor;
1437 
1438 
1439 /*
1440  * SVGA_CMD_UPDATE_VERBOSE --
1441  *
1442  *    Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1443  *    'reason' value, an opaque cookie which is used by internal
1444  *    debugging tools. Third party drivers should not use this
1445  *    command.
1446  *
1447  * Availability:
1448  *    SVGA_CAP_EXTENDED_FIFO
1449  */
1450 
1451 typedef
1452 struct {
1453    uint32 x;
1454    uint32 y;
1455    uint32 width;
1456    uint32 height;
1457    uint32 reason;
1458 } SVGAFifoCmdUpdateVerbose;
1459 
1460 
1461 /*
1462  * SVGA_CMD_FRONT_ROP_FILL --
1463  *
1464  *    This is a hint which tells the SVGA device that the driver has
1465  *    just filled a rectangular region of the GFB with a solid
1466  *    color. Instead of reading these pixels from the GFB, the device
1467  *    can assume that they all equal 'color'. This is primarily used
1468  *    for remote desktop protocols.
1469  *
1470  * Availability:
1471  *    SVGA_FIFO_CAP_ACCELFRONT
1472  */
1473 
1474 #define  SVGA_ROP_COPY                    0x03
1475 
1476 typedef
1477 struct {
1478    uint32 color;     /* In the same format as the GFB */
1479    uint32 x;
1480    uint32 y;
1481    uint32 width;
1482    uint32 height;
1483    uint32 rop;       /* Must be SVGA_ROP_COPY */
1484 } SVGAFifoCmdFrontRopFill;
1485 
1486 
1487 /*
1488  * SVGA_CMD_FENCE --
1489  *
1490  *    Insert a synchronization fence.  When the SVGA device reaches
1491  *    this command, it will copy the 'fence' value into the
1492  *    SVGA_FIFO_FENCE register. It will also compare the fence against
1493  *    SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1494  *    SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1495  *    raise this interrupt.
1496  *
1497  * Availability:
1498  *    SVGA_FIFO_FENCE for this command,
1499  *    SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1500  */
1501 
1502 typedef
1503 struct {
1504    uint32 fence;
1505 } SVGAFifoCmdFence;
1506 
1507 
1508 /*
1509  * SVGA_CMD_ESCAPE --
1510  *
1511  *    Send an extended or vendor-specific variable length command.
1512  *    This is used for video overlay, third party plugins, and
1513  *    internal debugging tools. See svga_escape.h
1514  *
1515  * Availability:
1516  *    SVGA_FIFO_CAP_ESCAPE
1517  */
1518 
1519 typedef
1520 struct {
1521    uint32 nsid;
1522    uint32 size;
1523    /* followed by 'size' bytes of data */
1524 } SVGAFifoCmdEscape;
1525 
1526 
1527 /*
1528  * SVGA_CMD_DEFINE_SCREEN --
1529  *
1530  *    Define or redefine an SVGAScreenObject. See the description of
1531  *    SVGAScreenObject above.  The video driver is responsible for
1532  *    generating new screen IDs. They should be small positive
1533  *    integers. The virtual device will have an implementation
1534  *    specific upper limit on the number of screen IDs
1535  *    supported. Drivers are responsible for recycling IDs. The first
1536  *    valid ID is zero.
1537  *
1538  *    - Interaction with other registers:
1539  *
1540  *    For backwards compatibility, when the GFB mode registers (WIDTH,
1541  *    HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1542  *    deletes all screens other than screen #0, and redefines screen
1543  *    #0 according to the specified mode. Drivers that use
1544  *    SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1545  *
1546  *    If you use screen objects, do not use the legacy multi-mon
1547  *    registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
1548  *
1549  * Availability:
1550  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1551  */
1552 
1553 typedef
1554 struct {
1555    SVGAScreenObject screen;   /* Variable-length according to version */
1556 } SVGAFifoCmdDefineScreen;
1557 
1558 
1559 /*
1560  * SVGA_CMD_DESTROY_SCREEN --
1561  *
1562  *    Destroy an SVGAScreenObject. Its ID is immediately available for
1563  *    re-use.
1564  *
1565  * Availability:
1566  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1567  */
1568 
1569 typedef
1570 struct {
1571    uint32 screenId;
1572 } SVGAFifoCmdDestroyScreen;
1573 
1574 
1575 /*
1576  * SVGA_CMD_DEFINE_GMRFB --
1577  *
1578  *    This command sets a piece of SVGA device state called the
1579  *    Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
1580  *    piece of light-weight state which identifies the location and
1581  *    format of an image in guest memory or in BAR1. The GMRFB has
1582  *    an arbitrary size, and it doesn't need to match the geometry
1583  *    of the GFB or any screen object.
1584  *
1585  *    The GMRFB can be redefined as often as you like. You could
1586  *    always use the same GMRFB, you could redefine it before
1587  *    rendering from a different guest screen, or you could even
1588  *    redefine it before every blit.
1589  *
1590  *    There are multiple ways to use this command. The simplest way is
1591  *    to use it to move the framebuffer either to elsewhere in the GFB
1592  *    (BAR1) memory region, or to a user-defined GMR. This lets a
1593  *    driver use a framebuffer allocated entirely out of normal system
1594  *    memory, which we encourage.
1595  *
1596  *    Another way to use this command is to set up a ring buffer of
1597  *    updates in GFB memory. If a driver wants to ensure that no
1598  *    frames are skipped by the SVGA device, it is important that the
1599  *    driver not modify the source data for a blit until the device is
1600  *    done processing the command. One efficient way to accomplish
1601  *    this is to use a ring of small DMA buffers. Each buffer is used
1602  *    for one blit, then we move on to the next buffer in the
1603  *    ring. The FENCE mechanism is used to protect each buffer from
1604  *    re-use until the device is finished with that buffer's
1605  *    corresponding blit.
1606  *
1607  *    This command does not affect the meaning of SVGA_CMD_UPDATE.
1608  *    UPDATEs always occur from the legacy GFB memory area. This
1609  *    command has no support for pseudocolor GMRFBs. Currently only
1610  *    true-color 15, 16, and 24-bit depths are supported. Future
1611  *    devices may expose capabilities for additional framebuffer
1612  *    formats.
1613  *
1614  *    The default GMRFB value is undefined. Drivers must always send
1615  *    this command at least once before performing any blit from the
1616  *    GMRFB.
1617  *
1618  * Availability:
1619  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1620  */
1621 
1622 typedef
1623 struct {
1624    SVGAGuestPtr        ptr;
1625    uint32              bytesPerLine;
1626    SVGAGMRImageFormat  format;
1627 } SVGAFifoCmdDefineGMRFB;
1628 
1629 
1630 /*
1631  * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
1632  *
1633  *    This is a guest-to-host blit. It performs a DMA operation to
1634  *    copy a rectangular region of pixels from the current GMRFB to
1635  *    one or more Screen Objects.
1636  *
1637  *    The destination coordinate may be specified relative to a
1638  *    screen's origin (if a screen ID is specified) or relative to the
1639  *    virtual coordinate system's origin (if the screen ID is
1640  *    SVGA_ID_INVALID). The actual destination may span zero or more
1641  *    screens, in the case of a virtual destination rect or a rect
1642  *    which extends off the edge of the specified screen.
1643  *
1644  *    This command writes to the screen's "base layer": the underlying
1645  *    framebuffer which exists below any cursor or video overlays. No
1646  *    action is necessary to explicitly hide or update any overlays
1647  *    which exist on top of the updated region.
1648  *
1649  *    The SVGA device is guaranteed to finish reading from the GMRFB
1650  *    by the time any subsequent FENCE commands are reached.
1651  *
1652  *    This command consumes an annotation. See the
1653  *    SVGA_CMD_ANNOTATION_* commands for details.
1654  *
1655  * Availability:
1656  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1657  */
1658 
1659 typedef
1660 struct {
1661    SVGASignedPoint  srcOrigin;
1662    SVGASignedRect   destRect;
1663    uint32           destScreenId;
1664 } SVGAFifoCmdBlitGMRFBToScreen;
1665 
1666 
1667 /*
1668  * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1669  *
1670  *    This is a host-to-guest blit. It performs a DMA operation to
1671  *    copy a rectangular region of pixels from a single Screen Object
1672  *    back to the current GMRFB.
1673  *
1674  *    Usage note: This command should be used rarely. It will
1675  *    typically be inefficient, but it is necessary for some types of
1676  *    synchronization between 3D (GPU) and 2D (CPU) rendering into
1677  *    overlapping areas of a screen.
1678  *
1679  *    The source coordinate is specified relative to a screen's
1680  *    origin. The provided screen ID must be valid. If any parameters
1681  *    are invalid, the resulting pixel values are undefined.
1682  *
1683  *    This command reads the screen's "base layer". Overlays like
1684  *    video and cursor are not included, but any data which was sent
1685  *    using a blit-to-screen primitive will be available, no matter
1686  *    whether the data's original source was the GMRFB or the 3D
1687  *    acceleration hardware.
1688  *
1689  *    Note that our guest-to-host blits and host-to-guest blits aren't
1690  *    symmetric in their current implementation. While the parameters
1691  *    are identical, host-to-guest blits are a lot less featureful.
1692  *    They do not support clipping: If the source parameters don't
1693  *    fully fit within a screen, the blit fails. They must originate
1694  *    from exactly one screen. Virtual coordinates are not directly
1695  *    supported.
1696  *
1697  *    Host-to-guest blits do support the same set of GMRFB formats
1698  *    offered by guest-to-host blits.
1699  *
1700  *    The SVGA device is guaranteed to finish writing to the GMRFB by
1701  *    the time any subsequent FENCE commands are reached.
1702  *
1703  * Availability:
1704  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1705  */
1706 
1707 typedef
1708 struct {
1709    SVGASignedPoint  destOrigin;
1710    SVGASignedRect   srcRect;
1711    uint32           srcScreenId;
1712 } SVGAFifoCmdBlitScreenToGMRFB;
1713 
1714 
1715 /*
1716  * SVGA_CMD_ANNOTATION_FILL --
1717  *
1718  *    This is a blit annotation. This command stores a small piece of
1719  *    device state which is consumed by the next blit-to-screen
1720  *    command. The state is only cleared by commands which are
1721  *    specifically documented as consuming an annotation. Other
1722  *    commands (such as ESCAPEs for debugging) may intervene between
1723  *    the annotation and its associated blit.
1724  *
1725  *    This annotation is a promise about the contents of the next
1726  *    blit: The video driver is guaranteeing that all pixels in that
1727  *    blit will have the same value, specified here as a color in
1728  *    SVGAColorBGRX format.
1729  *
1730  *    The SVGA device can still render the blit correctly even if it
1731  *    ignores this annotation, but the annotation may allow it to
1732  *    perform the blit more efficiently, for example by ignoring the
1733  *    source data and performing a fill in hardware.
1734  *
1735  *    This annotation is most important for performance when the
1736  *    user's display is being remoted over a network connection.
1737  *
1738  * Availability:
1739  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1740  */
1741 
1742 typedef
1743 struct {
1744    SVGAColorBGRX  color;
1745 } SVGAFifoCmdAnnotationFill;
1746 
1747 
1748 /*
1749  * SVGA_CMD_ANNOTATION_COPY --
1750  *
1751  *    This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
1752  *    information about annotations.
1753  *
1754  *    This annotation is a promise about the contents of the next
1755  *    blit: The video driver is guaranteeing that all pixels in that
1756  *    blit will have the same value as those which already exist at an
1757  *    identically-sized region on the same or a different screen.
1758  *
1759  *    Note that the source pixels for the COPY in this annotation are
1760  *    sampled before applying the anqnotation's associated blit. They
1761  *    are allowed to overlap with the blit's destination pixels.
1762  *
1763  *    The copy source rectangle is specified the same way as the blit
1764  *    destination: it can be a rectangle which spans zero or more
1765  *    screens, specified relative to either a screen or to the virtual
1766  *    coordinate system's origin. If the source rectangle includes
1767  *    pixels which are not from exactly one screen, the results are
1768  *    undefined.
1769  *
1770  * Availability:
1771  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1772  */
1773 
1774 typedef
1775 struct {
1776    SVGASignedPoint  srcOrigin;
1777    uint32           srcScreenId;
1778 } SVGAFifoCmdAnnotationCopy;
1779 
1780 
1781 /*
1782  * SVGA_CMD_DEFINE_GMR2 --
1783  *
1784  *    Define guest memory region v2.  See the description of GMRs above.
1785  *
1786  * Availability:
1787  *    SVGA_CAP_GMR2
1788  */
1789 
1790 typedef
1791 struct {
1792    uint32 gmrId;
1793    uint32 numPages;
1794 } SVGAFifoCmdDefineGMR2;
1795 
1796 
1797 /*
1798  * SVGA_CMD_REMAP_GMR2 --
1799  *
1800  *    Remap guest memory region v2.  See the description of GMRs above.
1801  *
1802  *    This command allows guest to modify a portion of an existing GMR by
1803  *    invalidating it or reassigning it to different guest physical pages.
1804  *    The pages are identified by physical page number (PPN).  The pages
1805  *    are assumed to be pinned and valid for DMA operations.
1806  *
1807  *    Description of command flags:
1808  *
1809  *    SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
1810  *       The PPN list must not overlap with the remap region (this can be
1811  *       handled trivially by referencing a separate GMR).  If flag is
1812  *       disabled, PPN list is appended to SVGARemapGMR command.
1813  *
1814  *    SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
1815  *       it is in PPN32 format.
1816  *
1817  *    SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
1818  *       A single PPN can be used to invalidate a portion of a GMR or
1819  *       map it to to a single guest scratch page.
1820  *
1821  * Availability:
1822  *    SVGA_CAP_GMR2
1823  */
1824 
1825 typedef enum {
1826    SVGA_REMAP_GMR2_PPN32         = 0,
1827    SVGA_REMAP_GMR2_VIA_GMR       = (1 << 0),
1828    SVGA_REMAP_GMR2_PPN64         = (1 << 1),
1829    SVGA_REMAP_GMR2_SINGLE_PPN    = (1 << 2),
1830 } SVGARemapGMR2Flags;
1831 
1832 typedef
1833 struct {
1834    uint32 gmrId;
1835    SVGARemapGMR2Flags flags;
1836    uint32 offsetPages; /* offset in pages to begin remap */
1837    uint32 numPages; /* number of pages to remap */
1838    /*
1839     * Followed by additional data depending on SVGARemapGMR2Flags.
1840     *
1841     * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
1842     * Otherwise an array of page descriptors in PPN32 or PPN64 format
1843     * (according to flag SVGA_REMAP_GMR2_PPN64) follows.  If flag
1844     * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
1845     */
1846 } SVGAFifoCmdRemapGMR2;
1847 
1848 
1849 /*
1850  * Size of SVGA device memory such as frame buffer and FIFO.
1851  */
1852 #define SVGA_VRAM_MIN_SIZE             (4 * 640 * 480) /* bytes */
1853 #define SVGA_VRAM_MIN_SIZE_3D       (16 * 1024 * 1024)
1854 #define SVGA_VRAM_MAX_SIZE         (128 * 1024 * 1024)
1855 #define SVGA_MEMORY_SIZE_MAX      (1024 * 1024 * 1024)
1856 #define SVGA_FIFO_SIZE_MAX           (2 * 1024 * 1024)
1857 #define SVGA_GRAPHICS_MEMORY_KB_MIN       (32 * 1024)
1858 #define SVGA_GRAPHICS_MEMORY_KB_MAX       (2 * 1024 * 1024)
1859 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT   (256 * 1024)
1860 
1861 #define SVGA_VRAM_SIZE_W2K          (64 * 1024 * 1024) /* 64 MB */
1862 
1863 /*
1864  * To simplify autoDetect display configuration, support a minimum of
1865  * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1866  *   numDisplays = 2
1867  *   maxWidth = numDisplay * 1920 = 3840
1868  *   maxHeight = rotated width of single monitor = 1920
1869  *   vramSize = maxWidth * maxHeight * 4 = 29491200
1870  */
1871 #define SVGA_VRAM_SIZE_AUTODETECT   (32 * 1024 * 1024)
1872 
1873 #if defined(VMX86_SERVER)
1874 #define SVGA_VRAM_SIZE               (4 * 1024 * 1024)
1875 #define SVGA_VRAM_SIZE_3D           (64 * 1024 * 1024)
1876 #define SVGA_FIFO_SIZE                    (256 * 1024)
1877 #define SVGA_FIFO_SIZE_3D                 (516 * 1024)
1878 #define SVGA_MEMORY_SIZE_DEFAULT   (160 * 1024 * 1024)
1879 #define SVGA_AUTODETECT_DEFAULT                  FALSE
1880 #else
1881 #define SVGA_VRAM_SIZE              (16 * 1024 * 1024)
1882 #define SVGA_VRAM_SIZE_3D           SVGA_VRAM_MAX_SIZE
1883 #define SVGA_FIFO_SIZE               (2 * 1024 * 1024)
1884 #define SVGA_FIFO_SIZE_3D               SVGA_FIFO_SIZE
1885 #define SVGA_MEMORY_SIZE_DEFAULT   (768 * 1024 * 1024)
1886 #define SVGA_AUTODETECT_DEFAULT                   TRUE
1887 #endif
1888 
1889 #endif
1890