| /external/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 248 Operand(current_input_offset(), SXTW)); in CheckCharacters()
321 Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
324 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
327 Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
331 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
368 Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
371 __ Cmp(current_input_offset().X(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
393 __ Add(x0, input_end(), Operand(capture_start_offset, SXTW)); in CheckNotBackReferenceIgnoreCase()
397 __ Add(x1, input_end(), Operand(current_input_offset(), SXTW)); in CheckNotBackReferenceIgnoreCase()
399 __ Sub(x1, x1, Operand(capture_length, SXTW)); in CheckNotBackReferenceIgnoreCase()
[all …]
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| /external/v8/src/arm64/ |
| D | codegen-arm64.cc | 179 __ Ldrh(result, MemOperand(string, index, SXTW, 1)); in Generate()
183 __ Ldrb(result, MemOperand(string, index, SXTW)); in Generate()
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| D | assembler-arm64-inl.h | 466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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| D | constants-arm64.h | 345 SXTW = 6, enumerator
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| D | disasm-arm64.cc | 1671 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | simulator-arm64.cc | 992 case SXTW: in ExtendValue()
1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | assembler-arm64.cc | 2505 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 47 SXTW, enumerator
66 case AArch64_AM::SXTW: return "sxtw"; in getShiftExtendName()
133 case 6: return AArch64_AM::SXTW; in getExtendType()
160 case AArch64_AM::SXTW: return 6; break; in getExtendEncoding()
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 336 (reg_.IsW() && ((extend_ == UXTW) || (extend_ == SXTW))))); in IsPlainRegister()
401 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
462 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
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| D | constants-aarch64.h | 291 SXTW = 6, enumerator
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| D | simulator-aarch64.cc | 409 case SXTW: in ExtendValue()
1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | disasm-aarch64.cc | 4773 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; in SubstituteLSRegOffsetField()
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| D | assembler-aarch64.cc | 4199 case SXTW: in EmitExtendShift()
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 194 COMPARE_MACRO(Mov(x16, Operand(x17, SXTW, 3)), "sbfiz x16, x17, #3, #32"); in TEST()
433 COMPARE(add(x24, x25, Operand(x26, SXTW, 1)), "add x24, x25, w26, sxtw #1"); in TEST()
459 COMPARE(sub(x24, x25, Operand(x26, SXTW, 1)), "sub x24, x25, w26, sxtw #1"); in TEST()
1056 COMPARE(ldr(w12, MemOperand(x13, w14, SXTW)), "ldr w12, [x13, w14, sxtw]"); in TEST()
1057 COMPARE(ldr(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1066 COMPARE(ldr(x12, MemOperand(x13, w14, SXTW)), "ldr x12, [x13, w14, sxtw]"); in TEST()
1067 COMPARE(ldr(x15, MemOperand(x16, w17, SXTW, 3)), in TEST()
1077 COMPARE(str(w12, MemOperand(x13, w14, SXTW)), "str w12, [x13, w14, sxtw]"); in TEST()
1078 COMPARE(str(w15, MemOperand(x16, w17, SXTW, 2)), in TEST()
1087 COMPARE(str(x12, MemOperand(x13, w14, SXTW)), "str x12, [x13, w14, sxtw]"); in TEST()
[all …]
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| D | test-assembler-aarch64.cc | 330 __ Mvn(x15, Operand(w2, SXTW, 4)); in TEST()
566 __ Mov(x30, Operand(x12, SXTW, 1)); in TEST()
641 __ Orr(x12, x0, Operand(x1, SXTW, 2)); in TEST()
735 __ Orn(x12, x0, Operand(x1, SXTW, 2)); in TEST()
802 __ And(x12, x0, Operand(x1, SXTW, 2)); in TEST()
940 __ Bic(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1064 __ Eor(x12, x0, Operand(x1, SXTW, 2)); in TEST()
1131 __ Eon(x12, x0, Operand(x1, SXTW, 2)); in TEST()
2661 __ Ldr(w3, MemOperand(x18, x27, SXTW)); in TEST()
2662 __ Ldr(w4, MemOperand(x18, x28, SXTW, 2)); in TEST()
[all …]
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| /external/v8/src/crankshaft/arm64/ |
| D | lithium-codegen-arm64.cc | 1360 right = Operand(ToRegister32(instr->right()), SXTW); in DoAddE()
1570 __ Ldr(scratch, MemOperand(elements, length, SXTW, kPointerSizeLog2)); in DoApplyArguments()
2762 __ Add(result, base, Operand(ToRegister32(instr->offset()), SXTW)); in DoInnerAllocatedObject()
3042 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3047 return MemOperand(scratch, key, SXTW, element_size_shift); in PrepareKeyedExternalArrayOperand()
3164 __ Add(base, elements, Operand(key, SXTW, element_size_shift)); in PrepareKeyedArrayOperand()
3168 return MemOperand(base, key, SXTW, element_size_shift); in PrepareKeyedArrayOperand()
3492 __ Cmp(result, Operand(result, SXTW)); in DoMathFloorI()
3766 __ Cmp(result, Operand(result.W(), SXTW)); in DoMathRoundI()
4061 __ Cmp(result.X(), Operand(result, SXTW)); in DoMulI()
[all …]
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 366 SXTW, enumerator
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 676 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
760 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
818 Addr.setExtendType(AArch64_AM::SXTW); in computeAddress()
990 if (Addr.getExtendType() == AArch64_AM::SXTW || in simplifyAddress()
1006 else if (Addr.getExtendType() == AArch64_AM::SXTW) in simplifyAddress()
1067 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW || in addLoadStoreOperands()
1771 Addr.getExtendType() == AArch64_AM::SXTW) in emitLoad()
2038 Addr.getExtendType() == AArch64_AM::SXTW) in emitStore()
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| D | AArch64ISelDAGToDAG.cpp | 381 return AArch64_AM::SXTW; in getExtendTypeForNode()
791 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectExtendedSHL()
860 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
872 SignExtend = CurDAG->getTargetConstant(Ext == AArch64_AM::SXTW, dl, in SelectAddrModeWRO()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || in isExtend()
1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && in isMemWExtend()
1577 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1589 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2395 .Case("sxtw", AArch64_AM::SXTW) in tryParseOptionalShiftExtend()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 123 return Operand(InputRegister32(index), SXTW); in InputOperand2_32()
153 return Operand(InputRegister64(index), SXTW); in InputOperand2_64()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1264 ### SXTW ### subsection
|