Searched refs:Shift1Reg (Results 1 – 2 of 2) sorted by relevance
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 4751 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local 4795 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitPartwordAtomicBinary() 4798 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); in EmitPartwordAtomicBinary() 5073 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local 5127 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitInstrWithCustomInserter() 5130 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); in EmitInstrWithCustomInserter()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 8542 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local 8586 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitPartwordAtomicBinary() 8589 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); in EmitPartwordAtomicBinary() 9257 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local 9311 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) in EmitInstrWithCustomInserter() 9314 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); in EmitInstrWithCustomInserter()
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